mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-28 02:24:53 +00:00
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
a0e221dc75
commit
1d9d7427c4
@ -27,8 +27,8 @@ enum PPCTargetEnum {
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};
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FunctionPass *createPPCBranchSelectionPass();
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FunctionPass *createPPC32ISelPattern(TargetMachine &TM);
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FunctionPass *createPPC32ISelDag(TargetMachine &TM);
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FunctionPass *createPPCISelPattern(TargetMachine &TM);
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FunctionPass *createPPCISelDag(TargetMachine &TM);
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FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
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FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
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@ -33,14 +33,14 @@ namespace {
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Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
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/// PPCDAGToDAGISel - PPC specific code to select PPC machine
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/// instructions for SelectionDAG operations.
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///
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class PPC32DAGToDAGISel : public SelectionDAGISel {
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class PPCDAGToDAGISel : public SelectionDAGISel {
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PPCTargetLowering PPCLowering;
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unsigned GlobalBaseReg;
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public:
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PPC32DAGToDAGISel(TargetMachine &TM)
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PPCDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
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virtual bool runOnFunction(Function &Fn) {
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@ -99,7 +99,7 @@ private:
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void PPC32DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// The selection process is inherently a bottom-up recursive process (users
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@ -156,13 +156,15 @@ void PPC32DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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/// getGlobalBaseReg - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
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SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
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if (!GlobalBaseReg) {
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = BB->getParent()->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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SSARegMap *RegMap = BB->getParent()->getSSARegMap();
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GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
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// FIXME: when we get to LP64, we will need to create the appropriate
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// type of register here.
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GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
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}
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@ -290,7 +292,7 @@ static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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/// 2. or and, shl 6. or shl, shr
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/// 3. or shr, and 7. or shr, shl
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/// 4. or and, shr
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SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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bool IsRotate = false;
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unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
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unsigned Value;
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@ -392,8 +394,8 @@ SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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/// SelectAddr - Given the specified address, return the two operands for a
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/// load/store instruction, and return true if it should be an indexed [r+r]
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/// operation.
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bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
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SDOperand &Op2) {
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bool PPCDAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
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SDOperand &Op2) {
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unsigned imm = 0;
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if (Addr.getOpcode() == ISD::ADD) {
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if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
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@ -445,8 +447,8 @@ bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
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/// SelectCC - Select a comparison of the specified values with the specified
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/// condition code, returning the CR# of the expression.
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SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
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ISD::CondCode CC) {
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SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
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ISD::CondCode CC) {
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// Always select the LHS.
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LHS = Select(LHS);
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@ -604,7 +606,7 @@ static struct mu magicu(unsigned d)
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
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SDOperand PPCDAGToDAGISel::BuildSDIVSequence(SDNode *N) {
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int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue();
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ms magics = magic(d);
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// Multiply the numerator (operand 0) by the magic value
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@ -630,7 +632,7 @@ SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
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SDOperand PPCDAGToDAGISel::BuildUDIVSequence(SDNode *N) {
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unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue();
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mu magics = magicu(d);
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// Multiply the numerator (operand 0) by the magic value
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@ -649,7 +651,7 @@ SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
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}
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}
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SDOperand PPC32DAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
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SDOperand PPCDAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
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SDNode *N = Op.Val;
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// FIXME: We are currently ignoring the requested alignment for handling
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@ -686,7 +688,7 @@ SDOperand PPC32DAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
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return SDOperand(Result.Val, Op.ResNo);
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}
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SDOperand PPC32DAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
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SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand LHSL = Select(N->getOperand(0));
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SDOperand LHSH = Select(N->getOperand(1));
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@ -729,7 +731,7 @@ SDOperand PPC32DAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
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CodeGenMap[Op.getValue(1)] = Result[1];
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return Result[Op.ResNo];
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}
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SDOperand PPC32DAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
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SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand LHSL = Select(N->getOperand(0));
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SDOperand LHSH = Select(N->getOperand(1));
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@ -746,7 +748,7 @@ SDOperand PPC32DAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
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return Result[Op.ResNo];
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}
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SDOperand PPC32DAGToDAGISel::SelectSETCC(SDOperand Op) {
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SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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SDNode *N = Op.Val;
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unsigned Imm;
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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@ -854,7 +856,7 @@ SDOperand PPC32DAGToDAGISel::SelectSETCC(SDOperand Op) {
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return SDOperand(N, 0);
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}
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SDOperand PPC32DAGToDAGISel::SelectCALL(SDOperand Op) {
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SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand Chain = Select(N->getOperand(0));
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@ -963,7 +965,7 @@ SDOperand PPC32DAGToDAGISel::SelectCALL(SDOperand Op) {
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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N->getOpcode() < PPCISD::FIRST_NUMBER)
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@ -1391,6 +1393,11 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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SDOperand Val = Select(N->getOperand(1));
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if (N->getOperand(1).getValueType() == MVT::i32) {
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Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
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} else if (N->getOperand(1).getValueType() == MVT::i64) {
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SDOperand Srl = CurDAG->getTargetNode(PPC::RLDICL, MVT::i64, Val,
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getI32Imm(32), getI32Imm(32));
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Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
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Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Srl);
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} else {
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assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
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Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
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@ -1465,10 +1472,10 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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/// createPPC32ISelDag - This pass converts a legalized DAG into a
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/// createPPCISelDag - This pass converts a legalized DAG into a
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/// PowerPC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
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return new PPC32DAGToDAGISel(TM);
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FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
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return new PPCDAGToDAGISel(TM);
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}
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@ -1,4 +1,4 @@
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//===-- PPCISelLowering.cpp - PPC32 DAG Lowering Implementation -----------===//
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//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -32,9 +32,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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setUseUnderscoreSetJmpLongJmp(true);
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// Set up the register classes.
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addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC32::F4RCRegisterClass);
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addRegisterClass(MVT::f64, PPC32::F8RCRegisterClass);
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addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
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addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
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// PowerPC has no intrinsics for these particular operations
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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@ -76,11 +76,6 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// PowerPC wants to expand i64 shifts itself.
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setOperationAction(ISD::SHL, MVT::i64, Custom);
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setOperationAction(ISD::SRL, MVT::i64, Custom);
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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// PowerPC does not have BRCOND* which requires SetCC
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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@ -98,11 +93,25 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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// PowerPC does not have truncstore for i1.
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setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
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// 64 bit PowerPC implementations have instructions to facilitate conversion
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// between i64 and fp.
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if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
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// 64 bit PowerPC implementations can support i64 types directly
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// FIXME: enable this once it works.
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//addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
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// They also have instructions for converting between i64 and fp.
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
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setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
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// 32 bit PowerPC wants to expand i64 shifts itself.
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// FIXME: remove these once we natively handle i64 shifts.
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setOperationAction(ISD::SHL, MVT::i64, Custom);
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setOperationAction(ISD::SRL, MVT::i64, Custom);
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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} else {
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// 32 bit PowerPC wants to expand i64 shifts itself.
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setOperationAction(ISD::SHL, MVT::i64, Custom);
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setOperationAction(ISD::SRL, MVT::i64, Custom);
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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}
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setSetCCResultContents(ZeroOrOneSetCCResult);
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@ -353,7 +362,7 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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ObjSize = 4;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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@ -371,7 +380,7 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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SDOperand argHi, argLo;
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unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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// If we have two or more remaining argument registers, then both halves
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@ -379,7 +388,7 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// have to come off the stack. This can happen when an i64 is preceded
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// by 28 bytes of arguments.
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if (GPR_remaining > 1) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx+1], VReg);
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argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
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} else {
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@ -402,9 +411,9 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (FPR_remaining > 0) {
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unsigned VReg;
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if (ObjectVT == MVT::f32)
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VReg = RegMap->createVirtualRegister(&PPC32::F4RCRegClass);
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VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
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else
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VReg = RegMap->createVirtualRegister(&PPC32::F8RCRegClass);
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VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
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MF.addLiveIn(FPR[FPR_idx], VReg);
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
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--FPR_remaining;
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@ -453,7 +462,7 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// result of va_next.
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std::vector<SDOperand> MemOps;
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for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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@ -84,7 +84,7 @@ public:
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// convenience functions for virtual register creation
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inline unsigned MakeIntReg() {
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return RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
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return RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
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}
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// dag -> dag expanders for integer divide by constant
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@ -591,7 +591,7 @@ unsigned ISel::SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC) {
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bool AlreadySelected = false;
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// Allocate a condition register for this expression
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Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
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Result = RegMap->createVirtualRegister(PPC::CRRCRegisterClass);
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// Use U to determine whether the SETCC immediate range is signed or not.
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bool U = ISD::isUnsignedIntSetCC(CC);
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@ -866,7 +866,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
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// Put a pointer to the space into the result register by copying the SP
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BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
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BuildMI(BB, PPC::OR4, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
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return Result;
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case ISD::ConstantPool:
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@ -996,7 +996,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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} else {
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::MTCTR, 1).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, PPC::OR4, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
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CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
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.addReg(PPC::R12);
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}
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@ -1013,7 +1013,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case MVT::i32:
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assert(GPR_idx < 8 && "Too many int args");
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if (N.getOperand(i+2).getOpcode() != ISD::UNDEF) {
|
||||
BuildMI(BB, PPC::OR,2,GPR[GPR_idx]).addReg(ArgVR[i]).addReg(ArgVR[i]);
|
||||
BuildMI(BB, PPC::OR4,2,GPR[GPR_idx]).addReg(ArgVR[i]).addReg(ArgVR[i]);
|
||||
CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
|
||||
}
|
||||
++GPR_idx;
|
||||
@ -1037,10 +1037,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
|
||||
case MVT::Other: return 1;
|
||||
case MVT::i32:
|
||||
if (Node->getValueType(1) == MVT::i32) {
|
||||
BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
|
||||
BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
|
||||
BuildMI(BB, PPC::OR4, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
|
||||
BuildMI(BB, PPC::OR4, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
|
||||
} else {
|
||||
BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
|
||||
BuildMI(BB, PPC::OR4, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
|
||||
}
|
||||
break;
|
||||
case MVT::f32:
|
||||
@ -1074,7 +1074,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
|
||||
ExprMap[N.getValue(1)] = 1;
|
||||
Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
||||
if (MVT::isInteger(DestType))
|
||||
BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
|
||||
BuildMI(BB, PPC::OR4, 2, Result).addReg(Tmp1).addReg(Tmp1);
|
||||
else if (DestType == MVT::f32)
|
||||
BuildMI(BB, PPC::FMRS, 1, Result).addReg(Tmp1);
|
||||
else
|
||||
@ -1144,7 +1144,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
|
||||
return Result;
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
BuildMI(BB, PPC::ADD4, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
return Result;
|
||||
|
||||
case ISD::FADD:
|
||||
@ -1250,7 +1250,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
|
||||
// emit regular or
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
Opc = Recording ? PPC::ORo : PPC::OR;
|
||||
Opc = Recording ? PPC::ORo : PPC::OR4;
|
||||
RecordSuccess = true;
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
return Result;
|
||||
@ -1755,7 +1755,7 @@ void ISel::Select(SDOperand N) {
|
||||
else if (N.getOperand(2).getValueType() == MVT::f32)
|
||||
BuildMI(BB, PPC::FMRS, 1, Tmp2).addReg(Tmp1);
|
||||
else
|
||||
BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
|
||||
BuildMI(BB, PPC::OR4, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
|
||||
}
|
||||
return;
|
||||
case ISD::ImplicitDef:
|
||||
@ -1779,8 +1779,8 @@ void ISel::Select(SDOperand N) {
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = SelectExpr(N.getOperand(1));
|
||||
Tmp2 = SelectExpr(N.getOperand(2));
|
||||
BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
|
||||
BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
|
||||
BuildMI(BB, PPC::OR4, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
|
||||
BuildMI(BB, PPC::OR4, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
|
||||
break;
|
||||
case 2:
|
||||
Select(N.getOperand(0));
|
||||
@ -1795,7 +1795,7 @@ void ISel::Select(SDOperand N) {
|
||||
BuildMI(BB, PPC::FMRS, 1, PPC::F1).addReg(Tmp1);
|
||||
break;
|
||||
case MVT::i32:
|
||||
BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
|
||||
BuildMI(BB, PPC::OR4, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
@ -1870,11 +1870,11 @@ void ISel::Select(SDOperand N) {
|
||||
}
|
||||
|
||||
|
||||
/// createPPC32PatternInstructionSelector - This pass converts an LLVM function
|
||||
/// createPPCPatternInstructionSelector - This pass converts an LLVM function
|
||||
/// into a machine code representation using pattern matching and a machine
|
||||
/// description file.
|
||||
///
|
||||
FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
|
||||
FunctionPass *llvm::createPPCISelPattern(TargetMachine &TM) {
|
||||
return new ISel(TM);
|
||||
}
|
||||
|
||||
|
||||
@ -25,7 +25,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
|
||||
unsigned& sourceReg,
|
||||
unsigned& destReg) const {
|
||||
MachineOpCode oc = MI.getOpcode();
|
||||
if (oc == PPC::OR) { // or r1, r2, r2
|
||||
if (oc == PPC::OR4 || oc == PPC::OR8) { // or r1, r2, r2
|
||||
assert(MI.getNumOperands() == 3 &&
|
||||
MI.getOperand(0).isRegister() &&
|
||||
MI.getOperand(1).isRegister() &&
|
||||
|
||||
@ -323,9 +323,12 @@ def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
"andc $rA, $rS, $rB",
|
||||
[(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
|
||||
def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
"or $rA, $rS, $rB",
|
||||
[(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
|
||||
def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
|
||||
"or $rA, $rS, $rB",
|
||||
[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
|
||||
def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
"nor $rA, $rS, $rB",
|
||||
[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
|
||||
@ -498,9 +501,12 @@ def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
|
||||
|
||||
// XO-Form instructions. Arithmetic instructions that can set overflow bit
|
||||
//
|
||||
def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"add $rT, $rA, $rB",
|
||||
[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
|
||||
def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
|
||||
"add $rT, $rA, $rB",
|
||||
[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
|
||||
def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
||||
"addc $rT, $rA, $rB",
|
||||
[]>;
|
||||
@ -648,6 +654,9 @@ let isTwoAddress = 1, isCommutable = 1 in {
|
||||
def RLWIMI : MForm_2<20,
|
||||
(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
|
||||
u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
|
||||
def RLDIMI : MDForm_1<30, 3,
|
||||
(ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
|
||||
"rldimi $rA, $rS, $SH, $MB">, isPPC64;
|
||||
}
|
||||
def RLWINM : MForm_2<21,
|
||||
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
||||
@ -662,10 +671,10 @@ def RLWNM : MForm_2<23,
|
||||
// MD-Form instructions. 64 bit rotate instructions.
|
||||
//
|
||||
def RLDICL : MDForm_1<30, 0,
|
||||
(ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
|
||||
(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
|
||||
"rldicl $rA, $rS, $SH, $MB">, isPPC64;
|
||||
def RLDICR : MDForm_1<30, 1,
|
||||
(ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
|
||||
(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
|
||||
"rldicr $rA, $rS, $SH, $ME">, isPPC64;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -40,7 +40,7 @@ PPCRegisterInfo::PPCRegisterInfo()
|
||||
ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
|
||||
ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
|
||||
ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
|
||||
ImmToIdxMap[PPC::ADDI] = PPC::ADD;
|
||||
ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
|
||||
}
|
||||
|
||||
void
|
||||
@ -51,14 +51,16 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
if (SrcReg == PPC::LR) {
|
||||
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
|
||||
} else if (RC == PPC32::CRRCRegisterClass) {
|
||||
} else if (RC == PPC::CRRCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
|
||||
} else if (RC == PPC32::GPRCRegisterClass) {
|
||||
} else if (RC == PPC::GPRCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
|
||||
} else if (RC == PPC32::F8RCRegisterClass) {
|
||||
} else if (RC == PPC::G8RCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
|
||||
} else if (RC == PPC::F8RCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
|
||||
} else if (RC == PPC32::F4RCRegisterClass) {
|
||||
} else if (RC == PPC::F4RCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
|
||||
} else {
|
||||
assert(0 && "Unknown regclass!");
|
||||
@ -74,14 +76,16 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
if (DestReg == PPC::LR) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
|
||||
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
|
||||
} else if (RC == PPC32::CRRCRegisterClass) {
|
||||
} else if (RC == PPC::CRRCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
|
||||
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
|
||||
} else if (RC == PPC32::GPRCRegisterClass) {
|
||||
} else if (RC == PPC::GPRCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
|
||||
} else if (RC == PPC32::F8RCRegisterClass) {
|
||||
} else if (RC == PPC::G8RCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
|
||||
} else if (RC == PPC::F8RCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
|
||||
} else if (RC == PPC32::F4RCRegisterClass) {
|
||||
} else if (RC == PPC::F4RCRegisterClass) {
|
||||
addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
|
||||
} else {
|
||||
assert(0 && "Unknown regclass!");
|
||||
@ -95,13 +99,15 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
const TargetRegisterClass *RC) const {
|
||||
MachineInstr *I;
|
||||
|
||||
if (RC == PPC32::GPRCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
|
||||
} else if (RC == PPC32::F4RCRegisterClass) {
|
||||
if (RC == PPC::GPRCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
|
||||
} else if (RC == PPC::G8RCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
|
||||
} else if (RC == PPC::F4RCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
|
||||
} else if (RC == PPC32::F8RCRegisterClass) {
|
||||
} else if (RC == PPC::F8RCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
|
||||
} else if (RC == PPC32::CRRCRegisterClass) {
|
||||
} else if (RC == PPC::CRRCRegisterClass) {
|
||||
BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
|
||||
} else {
|
||||
std::cerr << "Attempt to copy register that is not GPR or FPR";
|
||||
@ -113,6 +119,7 @@ unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
|
||||
int &FrameIndex) const {
|
||||
switch (MI->getOpcode()) {
|
||||
default: break;
|
||||
case PPC::LD:
|
||||
case PPC::LWZ:
|
||||
case PPC::LFS:
|
||||
case PPC::LFD:
|
||||
@ -135,7 +142,7 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
// it takes more than one instruction to store it.
|
||||
unsigned Opc = MI->getOpcode();
|
||||
|
||||
if ((Opc == PPC::OR &&
|
||||
if ((Opc == PPC::OR4 &&
|
||||
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
|
||||
if (OpNum == 0) { // move -> store
|
||||
unsigned InReg = MI->getOperand(1).getReg();
|
||||
@ -145,7 +152,16 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
unsigned OutReg = MI->getOperand(0).getReg();
|
||||
return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
|
||||
}
|
||||
|
||||
} else if ((Opc == PPC::OR8 &&
|
||||
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
|
||||
if (OpNum == 0) { // move -> store
|
||||
unsigned InReg = MI->getOperand(1).getReg();
|
||||
return addFrameReference(BuildMI(PPC::STD,
|
||||
3).addReg(InReg), FrameIndex);
|
||||
} else { // move -> load
|
||||
unsigned OutReg = MI->getOperand(0).getReg();
|
||||
return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
|
||||
}
|
||||
} else if (Opc == PPC::FMRD) {
|
||||
if (OpNum == 0) { // move -> store
|
||||
unsigned InReg = MI->getOperand(1).getReg();
|
||||
@ -315,7 +331,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
if (hasFP(MF)) {
|
||||
MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
|
||||
MI = BuildMI(PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
}
|
||||
|
||||
@ -87,7 +87,7 @@ def CTR : SPR<3, "ctr">;
|
||||
/// Register classes
|
||||
// Allocate volatiles first
|
||||
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
|
||||
def GPRC : RegisterClass<"PPC32", i32, 32,
|
||||
def GPRC : RegisterClass<"PPC", i32, 32,
|
||||
[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
|
||||
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
|
||||
R16, R15, R14, R13, R31, R0, R1, LR]>
|
||||
@ -110,13 +110,38 @@ def GPRC : RegisterClass<"PPC32", i32, 32,
|
||||
}
|
||||
}];
|
||||
}
|
||||
def G8RC : RegisterClass<"PPC", i64, 64,
|
||||
[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
|
||||
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
|
||||
R16, R15, R14, R13, R31, R0, R1, LR]>
|
||||
{
|
||||
let MethodProtos = [{
|
||||
iterator allocation_order_begin(MachineFunction &MF) const;
|
||||
iterator allocation_order_end(MachineFunction &MF) const;
|
||||
}];
|
||||
let MethodBodies = [{
|
||||
G8RCClass::iterator
|
||||
G8RCClass::allocation_order_begin(MachineFunction &MF) const {
|
||||
return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
|
||||
}
|
||||
G8RCClass::iterator
|
||||
G8RCClass::allocation_order_end(MachineFunction &MF) const {
|
||||
if (hasFP(MF))
|
||||
return end()-4;
|
||||
else
|
||||
return end()-3;
|
||||
}
|
||||
}];
|
||||
}
|
||||
|
||||
def F8RC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
|
||||
|
||||
def F8RC : RegisterClass<"PPC", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
|
||||
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
|
||||
def F4RC : RegisterClass<"PPC32", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
def F4RC : RegisterClass<"PPC", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
|
||||
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
|
||||
|
||||
|
||||
def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
|
||||
def CRRC : RegisterClass<"PPC", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
|
||||
|
||||
@ -99,9 +99,9 @@ bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
|
||||
|
||||
// Install an instruction selector.
|
||||
if (!DisablePPCDAGDAG)
|
||||
PM.add(createPPC32ISelDag(*this));
|
||||
PM.add(createPPCISelDag(*this));
|
||||
else
|
||||
PM.add(createPPC32ISelPattern(*this));
|
||||
PM.add(createPPCISelPattern(*this));
|
||||
|
||||
if (PrintMachineCode)
|
||||
PM.add(createMachineFunctionPrinterPass(&std::cerr));
|
||||
@ -156,9 +156,9 @@ void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
|
||||
// Install an instruction selector.
|
||||
if (!DisablePPCDAGDAG)
|
||||
PM.add(createPPC32ISelDag(TM));
|
||||
PM.add(createPPCISelDag(TM));
|
||||
else
|
||||
PM.add(createPPC32ISelPattern(TM));
|
||||
PM.add(createPPCISelPattern(TM));
|
||||
|
||||
PM.add(createRegisterAllocator());
|
||||
PM.add(createPrologEpilogCodeInserter());
|
||||
|
||||
Loading…
Reference in New Issue
Block a user