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transfer some notes from my email to somewhere useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25361 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -225,3 +225,29 @@ struct foo { double X, Y; };
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void xxx(struct foo F);
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void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
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===-------------------------------------------------------------------------===
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For this:
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int h(int i, int j, int k) {
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return (i==0||j==0||k == 0);
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}
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We currently emit this:
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_h:
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cntlzw r2, r3
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cntlzw r3, r4
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cntlzw r4, r5
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srwi r2, r2, 5
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srwi r3, r3, 5
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srwi r4, r4, 5
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or r2, r3, r2
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or r3, r2, r4
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blr
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The ctlz/shift instructions are created by the isel, so the dag combiner doesn't
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have a chance to pull the shifts through the or's (eliminating two
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instructions). SETCC nodes should be custom lowered in this case, not expanded
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by the isel.
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@ -54,6 +54,10 @@ fxch -> fucomi
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fucomi jl X
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jg X
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Ideas:
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http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html
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//===---------------------------------------------------------------------===//
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Improvements to the multiply -> shift/add algorithm:
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@ -121,3 +125,44 @@ Model X86 EFLAGS as a real register to avoid redudant cmp / test. e.g.
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setg %al
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testb %al, %al # unnecessary
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jne .BB7
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//===---------------------------------------------------------------------===//
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Count leading zeros and count trailing zeros:
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int clz(int X) { return __builtin_clz(X); }
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int ctz(int X) { return __builtin_ctz(X); }
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$ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
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clz:
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bsr %eax, DWORD PTR [%esp+4]
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xor %eax, 31
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ret
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ctz:
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bsf %eax, DWORD PTR [%esp+4]
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ret
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however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
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aren't.
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//===---------------------------------------------------------------------===//
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Use push/pop instructions in prolog/epilog sequences instead of stores off
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ESP (certain code size win, perf win on some [which?] processors).
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//===---------------------------------------------------------------------===//
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Only use inc/neg/not instructions on processors where they are faster than
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add/sub/xor. They are slower on the P4 due to only updating some processor
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flags.
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//===---------------------------------------------------------------------===//
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Open code rint,floor,ceil,trunc:
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html
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//===---------------------------------------------------------------------===//
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Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
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