6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

These two virtual methods are never called.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-29 05:59:33 +00:00
parent 0755912c38
commit 1ddf475b6a
8 changed files with 2 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -14,29 +14,10 @@
#include "SparcV8InstrInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "SparcV8GenInstrInfo.inc"
namespace llvm {
using namespace llvm;
SparcV8InstrInfo::SparcV8InstrInfo()
: TargetInstrInfo(SparcV8Insts,
sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
}
// createNOPinstr - returns the target's implementation of NOP, which is
// usually a pseudo-instruction, implemented by a degenerate version of
// another instruction.
//
MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
return 0;
}
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
//
bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
return false;
}
} // end namespace llvm

12
lib/Target/Sparc/SparcInstrInfo.h
View File

@ -29,18 +29,6 @@ public:
/// always be able to get register info as well (through this method).
///
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
/// createNOPinstr - returns the target's implementation of NOP, which is
/// usually a pseudo-instruction, implemented by a degenerate version of
/// another instruction.
///
MachineInstr* createNOPinstr() const;
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
///
bool isNOPinstr(const MachineInstr &MI) const;
};
}

21
lib/Target/SparcV8/SparcV8InstrInfo.cpp
View File

@ -14,29 +14,10 @@
#include "SparcV8InstrInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "SparcV8GenInstrInfo.inc"
namespace llvm {
using namespace llvm;
SparcV8InstrInfo::SparcV8InstrInfo()
: TargetInstrInfo(SparcV8Insts,
sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
}
// createNOPinstr - returns the target's implementation of NOP, which is
// usually a pseudo-instruction, implemented by a degenerate version of
// another instruction.
//
MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
return 0;
}
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
//
bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
return false;
}
} // end namespace llvm

12
lib/Target/SparcV8/SparcV8InstrInfo.h
View File

@ -29,18 +29,6 @@ public:
/// always be able to get register info as well (through this method).
///
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
/// createNOPinstr - returns the target's implementation of NOP, which is
/// usually a pseudo-instruction, implemented by a degenerate version of
/// another instruction.
///
MachineInstr* createNOPinstr() const;
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
///
bool isNOPinstr(const MachineInstr &MI) const;
};
}

1
lib/Target/X86/InstSelectSimple.cpp
View File

@ -23,7 +23,6 @@
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"

1
lib/Target/X86/X86ISelSimple.cpp
View File

@ -23,7 +23,6 @@
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"

27
lib/Target/X86/X86InstrInfo.cpp
View File

@ -24,33 +24,6 @@ X86InstrInfo::X86InstrInfo()
}
// createNOPinstr - returns the target's implementation of NOP, which is
// usually a pseudo-instruction, implemented by a degenerate version of
// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
//
MachineInstr* X86InstrInfo::createNOPinstr() const {
return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MachineOperand::UseAndDef)
.addReg(X86::AX, MachineOperand::UseAndDef);
}
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
//
bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
// Make sure the instruction is EXACTLY `xchg ax, ax'
if (MI.getOpcode() == X86::XCHGrr16) {
const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
if (op0.isRegister() && op0.getReg() == X86::AX &&
op1.isRegister() && op1.getReg() == X86::AX) {
return true;
}
}
// FIXME: there are several NOOP instructions, we should check for them here.
return false;
}
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {

12
lib/Target/X86/X86InstrInfo.h
View File

@ -178,12 +178,6 @@ public:
///
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
/// createNOPinstr - returns the target's implementation of NOP, which is
/// usually a pseudo-instruction, implemented by a degenerate version of
/// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
///
MachineInstr* createNOPinstr() const;
//
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
@ -192,12 +186,6 @@ public:
unsigned& sourceReg,
unsigned& destReg) const;
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
///
bool isNOPinstr(const MachineInstr &MI) const;
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified opcode number.
//