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Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70710 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2009-05-03 13:02:04 +00:00
parent 09c42f509a
commit 1df221f2bb
7 changed files with 97 additions and 11 deletions
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4
lib/Target/MSP430/MSP430ISelLowering.cpp
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@@ -39,7 +39,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
addRegisterClass(MVT::i16, MSP430::MSP430RegsRegisterClass);
addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
@@ -111,7 +111,7 @@ SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
abort();
case MVT::i16:
unsigned VReg =
RegInfo.createVirtualRegister(MSP430::MSP430RegsRegisterClass);
RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);