mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
- Various '#if 0' cleanups.
- Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction cleanups there as well. - Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better assist Chris to see the problem in bug 3101. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel
parent
845145f8b5
commit
1df30c4061
@ -124,6 +124,10 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
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setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
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// SMUL_LOHI, UMUL_LOHI are not legal for Cell:
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
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MVT StoreVT = (MVT::SimpleValueType) stype;
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setTruncStoreAction(VT, StoreVT, Expand);
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@ -207,7 +211,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// Custom lower i8, i32 and i64 multiplications
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setOperationAction(ISD::MUL, MVT::i8, Custom);
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setOperationAction(ISD::MUL, MVT::i32, Custom);
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setOperationAction(ISD::MUL, MVT::i32, Legal);
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setOperationAction(ISD::MUL, MVT::i64, Expand); // libcall
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// Need to custom handle (some) common i8, i64 math ops
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@ -239,8 +243,8 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::i8, Legal);
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setOperationAction(ISD::SETCC, MVT::i16, Legal);
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setOperationAction(ISD::SETCC, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::i64, Custom);
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setOperationAction(ISD::SETCC, MVT::i32, Legal);
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setOperationAction(ISD::SETCC, MVT::i64, Legal);
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// Zero extension and sign extension for i64 have to be
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// custom legalized
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@ -289,9 +293,9 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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++sctype) {
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MVT VT = (MVT::SimpleValueType)sctype;
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setOperationAction(ISD::GlobalAddress, VT, Custom);
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setOperationAction(ISD::ConstantPool, VT, Custom);
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setOperationAction(ISD::JumpTable, VT, Custom);
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setOperationAction(ISD::GlobalAddress, VT, Custom);
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setOperationAction(ISD::ConstantPool, VT, Custom);
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setOperationAction(ISD::JumpTable, VT, Custom);
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}
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// RET must be custom lowered, to meet ABI requirements
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@ -362,12 +366,15 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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}
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setOperationAction(ISD::MUL, MVT::v16i8, Custom);
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setOperationAction(ISD::AND, MVT::v16i8, Custom);
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setOperationAction(ISD::OR, MVT::v16i8, Custom);
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setOperationAction(ISD::XOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
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// FIXME: This is only temporary until I put all vector multiplications in
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// SPUInstrInfo.td:
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setOperationAction(ISD::MUL, MVT::v4i32, Legal);
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setShiftAmountType(MVT::i32);
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setBooleanContents(ZeroOrNegativeOneBooleanContent);
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@ -402,7 +409,7 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
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node_names[(unsigned) SPUISD::SHUFB] = "SPUISD::SHUFB";
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node_names[(unsigned) SPUISD::SHUFFLE_MASK] = "SPUISD::SHUFFLE_MASK";
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node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
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node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PROMOTE_SCALAR";
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node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PREFSLOT2VEC";
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node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT";
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node_names[(unsigned) SPUISD::MPY] = "SPUISD::MPY";
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node_names[(unsigned) SPUISD::MPYU] = "SPUISD::MPYU";
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@ -467,9 +474,9 @@ MVT SPUTargetLowering::getSetCCResultType(const SDValue &Op) const {
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emitted, e.g. for MVT::f32 extending load to MVT::f64:
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\verbatim
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%1 v16i8,ch = load
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%1 v16i8,ch = load
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%2 v16i8,ch = rotate %1
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%3 v4f8, ch = bitconvert %2
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%3 v4f8, ch = bitconvert %2
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%4 f32 = vec2perfslot %3
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%5 f64 = fp_extend %4
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\endverbatim
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@ -902,7 +909,7 @@ LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
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assert((FP != 0) &&
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"LowerConstantFP: Node is not ConstantFPSDNode");
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uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
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SDValue T = DAG.getConstant(dbits, MVT::i64);
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SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T);
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@ -936,7 +943,7 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) {
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return DAG.getNode(ISD::BRCOND, Op.getValueType(),
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Op.getOperand(0), Cond, Op.getOperand(2));
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}
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return SDValue(); // Unchanged
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}
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@ -1197,9 +1204,18 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// address pairs:
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Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, GA, Zero);
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}
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getExternalSymbol(S->getSymbol(), Callee.getValueType());
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else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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MVT CalleeVT = Callee.getValueType();
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SDValue Zero = DAG.getConstant(0, PtrVT);
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SDValue ExtSym = DAG.getTargetExternalSymbol(S->getSymbol(),
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Callee.getValueType());
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if (!ST->usingLargeMem()) {
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Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, ExtSym, Zero);
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} else {
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Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, ExtSym, Zero);
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}
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} else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
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// If this is an absolute destination address that appears to be a legal
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// local store address, use the munged value.
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Callee = SDValue(Dest, 0);
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@ -1831,7 +1847,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp);
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} else if (rotate) {
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int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
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return DAG.getNode(SPUISD::ROTBYTES_LEFT, V1.getValueType(),
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V1, DAG.getConstant(rotamt, MVT::i16));
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} else {
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@ -1915,17 +1931,8 @@ static SDValue LowerVectorMUL(SDValue Op, SelectionDAG &DAG) {
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abort();
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/*NOTREACHED*/
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case MVT::v4i32: {
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SDValue rA = Op.getOperand(0);
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SDValue rB = Op.getOperand(1);
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SDValue HiProd1 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rA, rB);
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SDValue HiProd2 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rB, rA);
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SDValue LoProd = DAG.getNode(SPUISD::MPYU, MVT::v4i32, rA, rB);
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SDValue Residual1 = DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd1);
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return DAG.getNode(ISD::ADD, MVT::v4i32, Residual1, HiProd2);
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break;
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}
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case MVT::v4i32:
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break;
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// Multiply two v8i16 vectors (pipeline friendly version):
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// a) multiply lower halves, mask off upper 16-bit of 32-bit product
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@ -2271,7 +2278,7 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
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SDValue result =
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DAG.getNode(SPUISD::SHUFB, VT,
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DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
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VecOp,
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VecOp,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
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return result;
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@ -2630,32 +2637,6 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
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return Op;
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}
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//! Lower i32 multiplication
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static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG, MVT VT,
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unsigned Opc) {
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switch (VT.getSimpleVT()) {
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default:
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cerr << "CellSPU: Unknown LowerMUL value type, got "
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<< Op.getValueType().getMVTString()
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<< "\n";
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abort();
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/*NOTREACHED*/
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case MVT::i32: {
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SDValue rA = Op.getOperand(0);
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SDValue rB = Op.getOperand(1);
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return DAG.getNode(ISD::ADD, MVT::i32,
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DAG.getNode(ISD::ADD, MVT::i32,
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DAG.getNode(SPUISD::MPYH, MVT::i32, rA, rB),
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DAG.getNode(SPUISD::MPYH, MVT::i32, rB, rA)),
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DAG.getNode(SPUISD::MPYU, MVT::i32, rA, rB));
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}
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}
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return SDValue();
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}
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//! Custom lowering for CTPOP (count population)
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/*!
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Custom lowering code that counts the number ones in the input
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@ -2951,8 +2932,6 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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return LowerVectorMUL(Op, DAG);
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else if (VT == MVT::i8)
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return LowerI8Math(Op, DAG, Opc, *this);
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else
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return LowerMUL(Op, DAG, VT, Opc);
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case ISD::FDIV:
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if (VT == MVT::f32 || VT == MVT::v4f32)
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@ -3030,7 +3009,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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|| Op1.getOpcode() == SPUISD::IndirectAddr) {
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// Normalize the operands to reduce repeated code
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SDValue IndirectArg = Op0, AddArg = Op1;
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if (Op1.getOpcode() == SPUISD::IndirectAddr) {
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IndirectArg = Op1;
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AddArg = Op0;
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@ -3160,9 +3139,9 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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case ISD::ANY_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::SIGN_EXTEND: {
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// (SPUpromote_scalar (any|zero|sign_extend (SPUvec2prefslot <arg>))) ->
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// (SPUprefslot2vec (any|zero|sign_extend (SPUvec2prefslot <arg>))) ->
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// <arg>
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// but only if the SPUpromote_scalar and <arg> types match.
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// but only if the SPUprefslot2vec and <arg> types match.
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SDValue Op00 = Op0.getOperand(0);
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if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) {
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SDValue Op000 = Op00.getOperand(0);
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@ -3173,7 +3152,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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break;
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}
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case SPUISD::VEC2PREFSLOT: {
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// (SPUpromote_scalar (SPUvec2prefslot <arg>)) ->
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// (SPUprefslot2vec (SPUvec2prefslot <arg>)) ->
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// <arg>
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Result = Op0.getOperand(0);
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break;
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@ -3329,7 +3308,7 @@ SPUTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
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}
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}
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}
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// LowerAsmOperandForConstraint
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void
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SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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@ -585,23 +585,29 @@ def AHIr16:
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"ahi\t$rT, $rA, $val", IntegerOp,
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[(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
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def Avec:
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RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"a\t$rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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class AInst<dag OOL, dag IOL, list<dag> pattern>:
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RRForm<0b00000011000, OOL, IOL,
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"a\t$rT, $rA, $rB", IntegerOp,
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pattern>;
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def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
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(Avec VECREG:$rA, VECREG:$rB)>;
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class AVecInst<ValueType vectype>:
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AInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (vectype VECREG:$rT), (add (vectype VECREG:$rA),
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(vectype VECREG:$rB)))]>;
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def Ar32:
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RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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"a\t$rT, $rA, $rB", IntegerOp,
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[(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
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class ARegInst<RegisterClass rclass>:
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AInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
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[(set rclass:$rT, (add rclass:$rA, rclass:$rB))]>;
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multiclass AddInstruction {
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def v4i32: AVecInst<v4i32>;
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def v16i8: AVecInst<v16i8>;
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def r32: ARegInst<R32C>;
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def r8: AInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB), [/* no pattern */]>;
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}
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def Ar8:
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RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
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"a\t$rT, $rA, $rB", IntegerOp,
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[/* no pattern */]>;
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defm A : AddInstruction;
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def AIvec:
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RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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@ -789,96 +795,109 @@ def BGXvec:
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def MPYv8i16:
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RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpy\t$rT, $rA, $rB", IntegerMulDiv,
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[(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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[(set (v8i16 VECREG:$rT), (SPUmpy_vec (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def MPYr16:
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RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
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"mpy\t$rT, $rA, $rB", IntegerMulDiv,
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[(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
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// Unsigned 16-bit multiply:
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class MPYUInst<dag OOL, dag IOL, list<dag> pattern>:
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RRForm<0b00110011110, OOL, IOL,
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"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
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pattern>;
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def MPYUv4i32:
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RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT),
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(SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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MPYUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (v4i32 VECREG:$rT),
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(SPUmpyu_vec (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def MPYUr16:
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RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
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"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
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[(set R32C:$rT, (mul (zext R16C:$rA),
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(zext R16C:$rB)))]>;
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MPYUInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
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[(set R32C:$rT, (mul (zext R16C:$rA), (zext R16C:$rB)))]>;
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def MPYUr32:
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RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
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[(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
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MPYUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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[(set R32C:$rT, (SPUmpyu_int R32C:$rA, R32C:$rB))]>;
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// mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
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// this only produces the lower 16 bits)
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def MPYIvec:
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RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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// mpyi: multiply 16 x s10imm -> 32 result.
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class MPYIInst<dag OOL, dag IOL, list<dag> pattern>:
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RI10Form<0b00101110, OOL, IOL,
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"mpyi\t$rT, $rA, $val", IntegerMulDiv,
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[(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
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pattern>;
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def MPYIvec:
|
||||
MPYIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
|
||||
[(set (v8i16 VECREG:$rT),
|
||||
(mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
|
||||
|
||||
def MPYIr16:
|
||||
RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
|
||||
"mpyi\t$rT, $rA, $val", IntegerMulDiv,
|
||||
[(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
|
||||
MPYIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
|
||||
[(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
|
||||
|
||||
// mpyui: same issues as other multiplies, plus, this doesn't match a
|
||||
// pattern... but may be used during target DAG selection or lowering
|
||||
|
||||
class MPYUIInst<dag OOL, dag IOL, list<dag> pattern>:
|
||||
RI10Form<0b10101110, OOL, IOL,
|
||||
"mpyui\t$rT, $rA, $val", IntegerMulDiv,
|
||||
pattern>;
|
||||
|
||||
def MPYUIvec:
|
||||
RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
|
||||
"mpyui\t$rT, $rA, $val", IntegerMulDiv,
|
||||
[]>;
|
||||
MPYUIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
|
||||
[]>;
|
||||
|
||||
def MPYUIr16:
|
||||
RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
|
||||
"mpyui\t$rT, $rA, $val", IntegerMulDiv,
|
||||
[]>;
|
||||
MPYUIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
|
||||
[]>;
|
||||
|
||||
// mpya: 16 x 16 + 16 -> 32 bit result
|
||||
class MPYAInst<dag OOL, dag IOL, list<dag> pattern>:
|
||||
RRRForm<0b0011, OOL, IOL,
|
||||
"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
|
||||
pattern>;
|
||||
|
||||
def MPYAvec:
|
||||
RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
|
||||
"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
|
||||
[(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
|
||||
(v8i16 VECREG:$rB)))),
|
||||
(v4i32 VECREG:$rC)))]>;
|
||||
MPYAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
|
||||
[(set (v4i32 VECREG:$rT),
|
||||
(add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
|
||||
(v8i16 VECREG:$rB)))),
|
||||
(v4i32 VECREG:$rC)))]>;
|
||||
|
||||
def MPYAr32:
|
||||
RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
|
||||
"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
|
||||
[(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
|
||||
R32C:$rC))]>;
|
||||
|
||||
def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
|
||||
(MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
|
||||
MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
|
||||
[(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
|
||||
R32C:$rC))]>;
|
||||
|
||||
def MPYAr32_sext:
|
||||
MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
|
||||
[(set R32C:$rT, (add (mul (sext R16C:$rA), (sext R16C:$rB)),
|
||||
R32C:$rC))]>;
|
||||
|
||||
def MPYAr32_sextinreg:
|
||||
RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
|
||||
"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
|
||||
[(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
|
||||
(sext_inreg R32C:$rB, i16)),
|
||||
R32C:$rC))]>;
|
||||
|
||||
//def MPYAr32:
|
||||
// RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
|
||||
// "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
|
||||
// [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
|
||||
// R32C:$rC))]>;
|
||||
MPYAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
|
||||
[(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
|
||||
(sext_inreg R32C:$rB, i16)),
|
||||
R32C:$rC))]>;
|
||||
|
||||
// mpyh: multiply high, used to synthesize 32-bit multiplies
|
||||
class MPYHInst<dag OOL, dag IOL, list<dag> pattern>:
|
||||
RRForm<0b10100011110, OOL, IOL,
|
||||
"mpyh\t$rT, $rA, $rB", IntegerMulDiv,
|
||||
pattern>;
|
||||
|
||||
def MPYHv4i32:
|
||||
RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"mpyh\t$rT, $rA, $rB", IntegerMulDiv,
|
||||
[(set (v4i32 VECREG:$rT),
|
||||
(SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
|
||||
MPYHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
[(set (v4i32 VECREG:$rT),
|
||||
(SPUmpyh_vec (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
|
||||
|
||||
def MPYHr32:
|
||||
RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
|
||||
"mpyh\t$rT, $rA, $rB", IntegerMulDiv,
|
||||
[(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
|
||||
MPYHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
|
||||
[(set R32C:$rT, (SPUmpyh_int R32C:$rA, R32C:$rB))]>;
|
||||
|
||||
// mpys: multiply high and shift right (returns the top half of
|
||||
// a 16-bit multiply, sign extended to 32 bits.)
|
||||
@ -898,7 +917,7 @@ def MPYHHv8i16:
|
||||
RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
|
||||
[(set (v8i16 VECREG:$rT),
|
||||
(SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
|
||||
(SPUmpyhh_vec (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
|
||||
|
||||
def MPYHHr32:
|
||||
RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
|
||||
@ -938,7 +957,26 @@ def MPYHHAUr32:
|
||||
"mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
|
||||
[]>;
|
||||
|
||||
//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
|
||||
// v4i32, i32 multiply instruction sequence:
|
||||
//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
|
||||
def MPYv4i32:
|
||||
Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
|
||||
(Av4i32
|
||||
(Av4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB),
|
||||
(MPYHv4i32 VECREG:$rB, VECREG:$rA)),
|
||||
(MPYUv4i32 VECREG:$rA, VECREG:$rB))>;
|
||||
|
||||
def MPYi32:
|
||||
Pat<(mul R32C:$rA, R32C:$rB),
|
||||
(Ar32
|
||||
(Ar32 (MPYHr32 R32C:$rA, R32C:$rB),
|
||||
(MPYHr32 R32C:$rB, R32C:$rA)),
|
||||
(MPYUr32 R32C:$rA, R32C:$rB))>;
|
||||
|
||||
//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
|
||||
// clz: Count leading zeroes
|
||||
//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
|
||||
class CLZInst<dag OOL, dag IOL, list<dag> pattern>:
|
||||
RRForm_1<0b10100101010, OOL, IOL, "clz\t$rT, $rA",
|
||||
IntegerOp, pattern>;
|
||||
@ -1803,8 +1841,8 @@ class SELBVecCondInst<ValueType vectype>:
|
||||
class SELBRegInst<RegisterClass rclass>:
|
||||
SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
|
||||
[(set rclass:$rT,
|
||||
(or (and rclass:$rA, rclass:$rC),
|
||||
(and rclass:$rB, (not rclass:$rC))))]>;
|
||||
(or (and rclass:$rB, rclass:$rC),
|
||||
(and rclass:$rA, (not rclass:$rC))))]>;
|
||||
|
||||
class SELBRegCondInst<RegisterClass rcond, RegisterClass rclass>:
|
||||
SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rcond:$rC),
|
||||
@ -3442,6 +3480,13 @@ let isCall = 1,
|
||||
BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
|
||||
}
|
||||
|
||||
// Support calls to external symbols:
|
||||
def : Pat<(SPUcall (SPUpcrel texternalsym:$func, 0)),
|
||||
(BRSL texternalsym:$func)>;
|
||||
|
||||
def : Pat<(SPUcall (SPUaform texternalsym:$func, 0)),
|
||||
(BRASL texternalsym:$func)>;
|
||||
|
||||
// Unconditional branches:
|
||||
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
|
||||
def BR :
|
||||
|
||||
@ -35,17 +35,12 @@ def SDT_SPUshuffle : SDTypeProfile<1, 3, [
|
||||
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
|
||||
]>;
|
||||
|
||||
// Unary, binary v16i8 operator type constraints:
|
||||
def SPUv16i8_binop: SDTypeProfile<1, 2, [
|
||||
SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
|
||||
// Vector binary operator type constraints (needs a further constraint to
|
||||
// ensure that operand 0 is a vector...):
|
||||
|
||||
// Binary v8i16 operator type constraints:
|
||||
def SPUv8i16_binop: SDTypeProfile<1, 2, [
|
||||
SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
|
||||
|
||||
// Binary v4i32 operator type constraints:
|
||||
def SPUv4i32_binop: SDTypeProfile<1, 2, [
|
||||
SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
|
||||
def SPUVecBinop: SDTypeProfile<1, 2, [
|
||||
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
|
||||
]>;
|
||||
|
||||
// Trinary operators, e.g., addx, carry generate
|
||||
def SPUIntTrinaryOp : SDTypeProfile<1, 3, [
|
||||
@ -93,23 +88,22 @@ def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>;
|
||||
def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
|
||||
|
||||
// SPU 16-bit multiply
|
||||
def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>;
|
||||
def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>;
|
||||
def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>;
|
||||
def SPUmpy_vec: SDNode<"SPUISD::MPY", SPUVecBinop, []>;
|
||||
|
||||
// SPU multiply unsigned, used in instruction lowering for v4i32
|
||||
// multiplies:
|
||||
def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>;
|
||||
def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
|
||||
def SPUmpyu_vec: SDNode<"SPUISD::MPYU", SPUVecBinop, []>;
|
||||
def SPUmpyu_int: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
|
||||
|
||||
// SPU 16-bit multiply high x low, shift result 16-bits
|
||||
// Used to compute intermediate products for 32-bit multiplies
|
||||
def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>;
|
||||
def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
|
||||
def SPUmpyh_vec: SDNode<"SPUISD::MPYH", SPUVecBinop, []>;
|
||||
def SPUmpyh_int: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
|
||||
|
||||
// SPU 16-bit multiply high x high, 32-bit product
|
||||
// Used to compute intermediate products for 16-bit multiplies
|
||||
def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>;
|
||||
def SPUmpyhh_vec: SDNode<"SPUISD::MPYHH", SPUVecBinop, []>;
|
||||
def SPUmpyhh_int: SDNode<"SPUISD::MPYHH", SDTIntBinOp, []>;
|
||||
|
||||
// Shift left quadword by bits and bytes
|
||||
def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user