mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Simplify copyConstantToRegister() for longs, using a pair of recursive calls.
Copy constant-pool entries' addresses into registers before loading out of them, to avoid errors from the assembler. Handle loading call args past the 6th one off the stack. Add IMPLICIT_DEF pseudo-instrs for double and long arguments passed in register pairs. Use FpMOVD to copy doubles around instead of the horrible store-load thing we were doing before. Handle 'ret double' and 'ret long'. Fix a bug in handling 'and/or/xor long'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16577 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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9b8ed0e04a
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@ -231,18 +231,10 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// Copy the value into the register pair.
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// R = top(more-significant) half, R+1 = bottom(less-significant) half
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uint64_t Val = cast<ConstantInt>(C)->getRawValue();
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unsigned bottomHalf = Val & 0xffffffffU;
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unsigned topHalf = Val >> 32;
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unsigned HH = topHalf >> 10;
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unsigned HM = topHalf & 0x03ff;
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unsigned LM = bottomHalf >> 10;
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unsigned LO = bottomHalf & 0x03ff;
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addZImm(HH);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addSImm (HM);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addZImm(LM);
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BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2)
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.addSImm (LO);
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copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
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Val >> 32), R);
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copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
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Val & 0xffffffffU), R+1);
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return;
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}
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@ -280,10 +272,14 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineConstantPool *CP = F->getConstantPool();
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unsigned CPI = CP->getConstantPoolIndex(CFP);
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const Type *Ty = CFP->getType();
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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unsigned AddrReg = makeAnotherReg (Type::UIntTy);
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
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BuildMI (*MBB, IP, LoadOpcode, 2, R).addConstantPoolIndex (CPI).addSImm (0);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
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BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg).addConstantPoolIndex (CPI);
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BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
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} else if (isa<ConstantPointerNull>(C)) {
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// Copy zero (null pointer) to the register.
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
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@ -304,12 +300,10 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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unsigned ArgOffset;
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static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
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V8::I3, V8::I4, V8::I5 };
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assert (LF->asize () < 7
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&& "Can't handle loading excess call args off the stack yet");
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// Add IMPLICIT_DEFs of input regs.
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ArgOffset = 0;
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for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
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for (Function::aiterator I = LF->abegin(), E = LF->aend();
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I != E && ArgOffset < 6; ++I, ++ArgOffset) {
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unsigned Reg = getReg(*I);
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switch (getClassB(I->getType())) {
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case cByte:
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@ -318,40 +312,75 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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case cFloat:
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
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break;
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case cDouble:
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case cLong:
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// Double and Long use register pairs.
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
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++ArgOffset;
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if (ArgOffset < 6)
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
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break;
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default:
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// FIXME: handle cDouble, cLong
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assert (0 && "64-bit (double, long, etc.) function args not handled");
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assert (0 && "type not handled");
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return;
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}
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++ArgOffset;
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}
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ArgOffset = 0;
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for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
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for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E;
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++I, ++ArgOffset) {
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unsigned Reg = getReg(*I);
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switch (getClassB(I->getType())) {
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case cByte:
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case cShort:
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case cInt:
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BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
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.addReg (IncomingArgRegs[ArgOffset]);
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break;
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case cFloat: {
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// Single-fp args are passed in integer registers; go through
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// memory to get them into FP registers. (Bleh!)
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unsigned FltAlign = TM.getTargetData().getFloatAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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.addReg (IncomingArgRegs[ArgOffset]);
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BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
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break;
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if (ArgOffset < 6) {
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switch (getClassB(I->getType())) {
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case cByte:
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case cShort:
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case cInt:
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BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
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.addReg (IncomingArgRegs[ArgOffset]);
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break;
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case cFloat: {
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// Single-fp args are passed in integer registers; go through
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// memory to get them into FP registers. (Bleh!)
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unsigned FltAlign = TM.getTargetData().getFloatAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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.addReg (IncomingArgRegs[ArgOffset]);
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BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
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break;
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}
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default:
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// FIXME: handle cDouble, cLong
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assert (0 && "64-bit (double, long, etc.) function args not handled");
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return;
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}
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} else {
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switch (getClassB(I->getType())) {
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case cByte:
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case cShort:
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case cInt: {
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int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
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BuildMI (BB, V8::LD, 2, Reg).addFrameIndex (FI).addSImm(0);
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break;
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}
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case cFloat: {
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int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
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BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
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break;
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}
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case cDouble: {
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int FI = F->getFrameInfo()->CreateFixedObject(8, 68 + (4 * ArgOffset));
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BuildMI (BB, V8::LDDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
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break;
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}
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default:
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// FIXME: handle cLong
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assert (0 && "64-bit integer (long/ulong) function args not handled");
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return;
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}
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}
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default:
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// FIXME: handle cDouble, cLong
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assert (0 && "64-bit (double, long, etc.) function args not handled");
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return;
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}
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++ArgOffset;
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}
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}
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@ -574,16 +603,9 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
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case cFloat:
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BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
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break;
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case cDouble: {
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// go through memory, for now
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unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
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BuildMI (*BB, IP, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (SrcReg);
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BuildMI (*BB, IP, V8::LDDFri, 2, DestReg).addFrameIndex (FI)
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.addSImm (0);
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case cDouble: // use double move pseudo-instr
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BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
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break;
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}
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default: {
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unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
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unsigned TmpReg = makeAnotherReg (newTy);
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@ -712,6 +734,18 @@ void V8ISel::visitCallInst(CallInst &I) {
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.addReg (ArgReg);
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BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
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.addSImm (0);
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} else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
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// Double-fp args are passed in pairs of integer registers; go through
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// memory to get them out of FP registers. (Bleh!)
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assert (i <= 5 && "Can't deal with double-fp args past #5 yet");
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unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
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BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (ArgReg);
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BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
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.addSImm (0);
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BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i]).addFrameIndex (FI)
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.addSImm (4);
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} else {
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assert (0 && "64-bit (double, long, etc.) 'call' opnds not handled");
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}
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@ -738,6 +772,13 @@ void V8ISel::visitCallInst(CallInst &I) {
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case cFloat:
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BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
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break;
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case cDouble:
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BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
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break;
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case cLong:
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BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
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BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
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break;
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default:
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std::cerr << "Return type of call instruction not handled: " << I;
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abort ();
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@ -755,16 +796,11 @@ void V8ISel::visitReturnInst(ReturnInst &I) {
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BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
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break;
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case cFloat:
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BuildMI (BB, V8::FMOVS, 2, V8::F0).addReg(RetValReg);
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BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
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break;
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case cDouble: {
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unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
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BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (RetValReg);
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BuildMI (BB, V8::LDDFri, 2, V8::F0).addFrameIndex (FI).addSImm (0);
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case cDouble:
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BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
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break;
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}
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case cLong:
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BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
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BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
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@ -900,10 +936,18 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
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}
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unsigned ResultReg = DestReg;
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if (Class != cInt)
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if (Class != cInt && Class != cLong)
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ResultReg = makeAnotherReg (I.getType ());
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// FIXME: support long, ulong, fp.
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if (Class == cLong) {
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DEBUG (std::cerr << "Class = cLong\n");
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DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
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DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
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DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
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DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
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}
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// FIXME: support long, ulong.
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switch (I.getOpcode ()) {
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case Instruction::Add: OpCase = 0; break;
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case Instruction::Sub: OpCase = 1; break;
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@ -231,18 +231,10 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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// Copy the value into the register pair.
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// R = top(more-significant) half, R+1 = bottom(less-significant) half
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uint64_t Val = cast<ConstantInt>(C)->getRawValue();
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unsigned bottomHalf = Val & 0xffffffffU;
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unsigned topHalf = Val >> 32;
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unsigned HH = topHalf >> 10;
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unsigned HM = topHalf & 0x03ff;
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unsigned LM = bottomHalf >> 10;
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unsigned LO = bottomHalf & 0x03ff;
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addZImm(HH);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addSImm (HM);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addZImm(LM);
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BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2)
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.addSImm (LO);
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copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
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Val >> 32), R);
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copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
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Val & 0xffffffffU), R+1);
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return;
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}
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@ -280,10 +272,14 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineConstantPool *CP = F->getConstantPool();
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unsigned CPI = CP->getConstantPoolIndex(CFP);
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const Type *Ty = CFP->getType();
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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unsigned AddrReg = makeAnotherReg (Type::UIntTy);
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
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BuildMI (*MBB, IP, LoadOpcode, 2, R).addConstantPoolIndex (CPI).addSImm (0);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
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BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg).addConstantPoolIndex (CPI);
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BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
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} else if (isa<ConstantPointerNull>(C)) {
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// Copy zero (null pointer) to the register.
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
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@ -304,12 +300,10 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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unsigned ArgOffset;
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static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
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V8::I3, V8::I4, V8::I5 };
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assert (LF->asize () < 7
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&& "Can't handle loading excess call args off the stack yet");
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// Add IMPLICIT_DEFs of input regs.
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ArgOffset = 0;
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for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
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for (Function::aiterator I = LF->abegin(), E = LF->aend();
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I != E && ArgOffset < 6; ++I, ++ArgOffset) {
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unsigned Reg = getReg(*I);
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switch (getClassB(I->getType())) {
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case cByte:
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@ -318,40 +312,75 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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case cFloat:
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
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break;
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case cDouble:
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case cLong:
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// Double and Long use register pairs.
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
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++ArgOffset;
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if (ArgOffset < 6)
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
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break;
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default:
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// FIXME: handle cDouble, cLong
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assert (0 && "64-bit (double, long, etc.) function args not handled");
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assert (0 && "type not handled");
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return;
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}
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++ArgOffset;
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}
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ArgOffset = 0;
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for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
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for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E;
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++I, ++ArgOffset) {
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unsigned Reg = getReg(*I);
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switch (getClassB(I->getType())) {
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case cByte:
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case cShort:
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case cInt:
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BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
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.addReg (IncomingArgRegs[ArgOffset]);
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break;
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case cFloat: {
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// Single-fp args are passed in integer registers; go through
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// memory to get them into FP registers. (Bleh!)
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unsigned FltAlign = TM.getTargetData().getFloatAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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.addReg (IncomingArgRegs[ArgOffset]);
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BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
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break;
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if (ArgOffset < 6) {
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switch (getClassB(I->getType())) {
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case cByte:
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case cShort:
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case cInt:
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BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
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.addReg (IncomingArgRegs[ArgOffset]);
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break;
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case cFloat: {
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// Single-fp args are passed in integer registers; go through
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// memory to get them into FP registers. (Bleh!)
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unsigned FltAlign = TM.getTargetData().getFloatAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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.addReg (IncomingArgRegs[ArgOffset]);
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BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
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break;
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}
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default:
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// FIXME: handle cDouble, cLong
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assert (0 && "64-bit (double, long, etc.) function args not handled");
|
||||
return;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
switch (getClassB(I->getType())) {
|
||||
case cByte:
|
||||
case cShort:
|
||||
case cInt: {
|
||||
int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
|
||||
BuildMI (BB, V8::LD, 2, Reg).addFrameIndex (FI).addSImm(0);
|
||||
break;
|
||||
}
|
||||
case cFloat: {
|
||||
int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
|
||||
BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
|
||||
break;
|
||||
}
|
||||
case cDouble: {
|
||||
int FI = F->getFrameInfo()->CreateFixedObject(8, 68 + (4 * ArgOffset));
|
||||
BuildMI (BB, V8::LDDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
// FIXME: handle cLong
|
||||
assert (0 && "64-bit integer (long/ulong) function args not handled");
|
||||
return;
|
||||
}
|
||||
}
|
||||
default:
|
||||
// FIXME: handle cDouble, cLong
|
||||
assert (0 && "64-bit (double, long, etc.) function args not handled");
|
||||
return;
|
||||
}
|
||||
++ArgOffset;
|
||||
}
|
||||
|
||||
}
|
||||
@ -574,16 +603,9 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
|
||||
case cFloat:
|
||||
BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
|
||||
break;
|
||||
case cDouble: {
|
||||
// go through memory, for now
|
||||
unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
|
||||
int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
|
||||
BuildMI (*BB, IP, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
|
||||
.addReg (SrcReg);
|
||||
BuildMI (*BB, IP, V8::LDDFri, 2, DestReg).addFrameIndex (FI)
|
||||
.addSImm (0);
|
||||
case cDouble: // use double move pseudo-instr
|
||||
BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
|
||||
unsigned TmpReg = makeAnotherReg (newTy);
|
||||
@ -712,6 +734,18 @@ void V8ISel::visitCallInst(CallInst &I) {
|
||||
.addReg (ArgReg);
|
||||
BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
|
||||
.addSImm (0);
|
||||
} else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
|
||||
// Double-fp args are passed in pairs of integer registers; go through
|
||||
// memory to get them out of FP registers. (Bleh!)
|
||||
assert (i <= 5 && "Can't deal with double-fp args past #5 yet");
|
||||
unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
|
||||
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
||||
BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
|
||||
.addReg (ArgReg);
|
||||
BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
|
||||
.addSImm (0);
|
||||
BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i]).addFrameIndex (FI)
|
||||
.addSImm (4);
|
||||
} else {
|
||||
assert (0 && "64-bit (double, long, etc.) 'call' opnds not handled");
|
||||
}
|
||||
@ -738,6 +772,13 @@ void V8ISel::visitCallInst(CallInst &I) {
|
||||
case cFloat:
|
||||
BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
|
||||
break;
|
||||
case cDouble:
|
||||
BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
|
||||
break;
|
||||
case cLong:
|
||||
BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
|
||||
BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
|
||||
break;
|
||||
default:
|
||||
std::cerr << "Return type of call instruction not handled: " << I;
|
||||
abort ();
|
||||
@ -755,16 +796,11 @@ void V8ISel::visitReturnInst(ReturnInst &I) {
|
||||
BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
|
||||
break;
|
||||
case cFloat:
|
||||
BuildMI (BB, V8::FMOVS, 2, V8::F0).addReg(RetValReg);
|
||||
BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
|
||||
break;
|
||||
case cDouble: {
|
||||
unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
|
||||
int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
|
||||
BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
|
||||
.addReg (RetValReg);
|
||||
BuildMI (BB, V8::LDDFri, 2, V8::F0).addFrameIndex (FI).addSImm (0);
|
||||
case cDouble:
|
||||
BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
|
||||
break;
|
||||
}
|
||||
case cLong:
|
||||
BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
|
||||
BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
|
||||
@ -900,10 +936,18 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
|
||||
}
|
||||
|
||||
unsigned ResultReg = DestReg;
|
||||
if (Class != cInt)
|
||||
if (Class != cInt && Class != cLong)
|
||||
ResultReg = makeAnotherReg (I.getType ());
|
||||
|
||||
// FIXME: support long, ulong, fp.
|
||||
if (Class == cLong) {
|
||||
DEBUG (std::cerr << "Class = cLong\n");
|
||||
DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
|
||||
DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
|
||||
DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
|
||||
DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
|
||||
}
|
||||
|
||||
// FIXME: support long, ulong.
|
||||
switch (I.getOpcode ()) {
|
||||
case Instruction::Add: OpCase = 0; break;
|
||||
case Instruction::Sub: OpCase = 1; break;
|
||||
|
Loading…
Reference in New Issue
Block a user