diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index cb71453fc9c..b212d8d8639 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1232,12 +1232,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { } } -// On non-Darwin platforms R9 is callee-saved. +// All calls clobber the non-callee saved registers. SP is marked as +// a use to prevent stack-pointer assignments that appear immediately +// before calls from potentially appearing dead. let isCall = 1, + // On non-Darwin platforms R9 is callee-saved. Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, - D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { + D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR], + Uses = [SP] in { def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, @@ -1288,12 +1292,15 @@ let isCall = 1, } } -// On Darwin R9 is call-clobbered. let isCall = 1, + // On Darwin R9 is call-clobbered. + // R7 is marked as a use to prevent frame-pointer assignments from being + // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, - D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { + D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR], + Uses = [R7, SP] in { def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> { @@ -1473,7 +1480,7 @@ def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", } // Supervisor Call (Software Interrupt) -- for disassembly only -let isCall = 1 in { +let isCall = 1, Uses = [SP] in { def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", [/* For disassembly only; pattern left blank */]> { bits<24> svc; @@ -3241,7 +3248,7 @@ def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb", // FIXME: This needs to be a pseudo of some sort so that we can get the // encoding right, complete with fixup for the aeabi_read_tp function. let isCall = 1, - Defs = [R0, R12, LR, CPSR] in { + Defs = [R0, R12, LR, CPSR], Uses = [SP] in { def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br, "bl\t__aeabi_read_tp", [(set R0, ARMthread_pointer)]>; diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 5dae5bd7a9b..4c94f60e222 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -336,11 +336,16 @@ def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), let Inst{7-0} = regs{7-0}; } +// All calls clobber the non-callee saved registers. SP is marked as +// a use to prevent stack-pointer assignments that appear immediately +// before calls from potentially appearing dead. let isCall = 1, + // On non-Darwin platforms R9 is callee-saved. Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, - D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { + D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR], + Uses = [SP] in { // Also used for Thumb2 def tBL : TIx2<0b11110, 0b11, 1, (outs), (ins i32imm:$func, variable_ops), IIC_Br, @@ -371,12 +376,15 @@ let isCall = 1, Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; } -// On Darwin R9 is call-clobbered. let isCall = 1, + // On Darwin R9 is call-clobbered. + // R7 is marked as a use to prevent frame-pointer assignments from being + // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, - D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { + D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR], + Uses = [R7, SP] in { // Also used for Thumb2 def tBLr9 : TIx2<0b11110, 0b11, 1, (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br, @@ -469,7 +477,7 @@ let isBranch = 1, isTerminator = 1 in { // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only // A8.6.16 B: Encoding T1 // If Inst{11-8} == 0b1111 then SEE SVC -let isCall = 1 in +let isCall = 1, Uses = [SP] in def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br, "svc", "\t$imm", []>, Encoding16 { bits<8> imm; @@ -1250,7 +1258,7 @@ def tLEApcrelJT : T1I<(outs tGPR:$dst), // __aeabi_read_tp preserves the registers r1-r3. let isCall = 1, - Defs = [R0, LR] in { + Defs = [R0, LR], Uses = [SP] in { def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br, "bl\t__aeabi_read_tp", [(set R0, ARMthread_pointer)]>; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index cef207fd52a..fadc7102794 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -2836,7 +2836,7 @@ def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", // __aeabi_read_tp preserves the registers r1-r3. let isCall = 1, - Defs = [R0, R12, LR, CPSR] in { + Defs = [R0, R12, LR, CPSR], Uses = [SP] in { def t2TPsoft : T2XI<(outs), (ins), IIC_Br, "bl\t__aeabi_read_tp", [(set R0, ARMthread_pointer)]> { diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll new file mode 100644 index 00000000000..8d7541feae9 --- /dev/null +++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB2 +; rdar://8690640 + +define i32* @t(i32* %x) nounwind { +entry: +; ARM: t: +; ARM: push +; ARM: mov r7, sp +; ARM: bl _foo +; ARM: bl _foo +; ARM: bl _foo +; ARM: ldmia sp!, {r7, pc} + +; THUMB2: t: +; THUMB2: push +; THUMB2: mov r7, sp +; THUMB2: blx _foo +; THUMB2: blx _foo +; THUMB2: blx _foo +; THUMB2: pop + %0 = tail call i32* @foo(i32* %x) nounwind + %1 = tail call i32* @foo(i32* %0) nounwind + %2 = tail call i32* @foo(i32* %1) nounwind + ret i32* %2 +} + +declare i32* @foo(i32*)