mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Tidy up formatting a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
95102265a9
commit
1e0fff17f3
@ -14,18 +14,18 @@ _func:
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@------------------------------------------------------------------------------
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@ ADC (immediate)
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@------------------------------------------------------------------------------
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adc r1, r2, #0xf
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adc r1, r2, #0xf0
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adc r1, r2, #0xf00
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adc r1, r2, #0xf000
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adc r1, r2, #0xf0000
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adc r1, r2, #0xf00000
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adc r1, r2, #0xf000000
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adc r1, r2, #0xf0000000
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adc r1, r2, #0xf000000f
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adcs r1, r2, #0xf00
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adcseq r1, r2, #0xf00
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adceq r1, r2, #0xf00
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adc r1, r2, #0xf
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adc r1, r2, #0xf0
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adc r1, r2, #0xf00
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adc r1, r2, #0xf000
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adc r1, r2, #0xf0000
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adc r1, r2, #0xf00000
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adc r1, r2, #0xf000000
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adc r1, r2, #0xf0000000
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adc r1, r2, #0xf000000f
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adcs r1, r2, #0xf00
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adcseq r1, r2, #0xf00
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adceq r1, r2, #0xf00
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@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
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@ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
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@ -45,44 +45,44 @@ _func:
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@ ADC (register)
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@ ADC (shifted register)
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@------------------------------------------------------------------------------
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adc r4, r5, r6
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@ Constant shifts
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adc r4, r5, r6, lsl #1
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adc r4, r5, r6, lsl #31
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adc r4, r5, r6, lsr #1
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adc r4, r5, r6, lsr #31
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adc r4, r5, r6, lsr #32
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adc r4, r5, r6, asr #1
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adc r4, r5, r6, asr #31
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adc r4, r5, r6, asr #32
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adc r4, r5, r6, ror #1
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adc r4, r5, r6, ror #31
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adc r4, r5, r6
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@ Constant shifts
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adc r4, r5, r6, lsl #1
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adc r4, r5, r6, lsl #31
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adc r4, r5, r6, lsr #1
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adc r4, r5, r6, lsr #31
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adc r4, r5, r6, lsr #32
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adc r4, r5, r6, asr #1
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adc r4, r5, r6, asr #31
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adc r4, r5, r6, asr #32
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adc r4, r5, r6, ror #1
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adc r4, r5, r6, ror #31
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@ Register shifts
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adc r6, r7, r8, lsl r9
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adc r6, r7, r8, lsr r9
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adc r6, r7, r8, asr r9
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adc r6, r7, r8, ror r9
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adc r4, r5, r6, rrx
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@ Register shifts
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adc r6, r7, r8, lsl r9
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adc r6, r7, r8, lsr r9
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adc r6, r7, r8, asr r9
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adc r6, r7, r8, ror r9
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adc r4, r5, r6, rrx
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@ Destination register is optional
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adc r5, r6
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adc r4, r5, lsl #1
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adc r4, r5, lsl #31
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adc r4, r5, lsr #1
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adc r4, r5, lsr #31
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adc r4, r5, lsr #32
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adc r4, r5, asr #1
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adc r4, r5, asr #31
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adc r4, r5, asr #32
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adc r4, r5, ror #1
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adc r4, r5, ror #31
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adc r4, r5, rrx
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adc r6, r7, lsl r9
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adc r6, r7, lsr r9
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adc r6, r7, asr r9
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adc r6, r7, ror r9
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adc r4, r5, rrx
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@ Destination register is optional
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adc r5, r6
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adc r4, r5, lsl #1
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adc r4, r5, lsl #31
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adc r4, r5, lsr #1
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adc r4, r5, lsr #31
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adc r4, r5, lsr #32
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adc r4, r5, asr #1
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adc r4, r5, asr #31
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adc r4, r5, asr #32
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adc r4, r5, ror #1
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adc r4, r5, ror #31
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adc r4, r5, rrx
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adc r6, r7, lsl r9
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adc r6, r7, lsr r9
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adc r6, r7, asr r9
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adc r6, r7, ror r9
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adc r4, r5, rrx
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@ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0]
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@ -126,11 +126,11 @@ _func:
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@ ADR
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@------------------------------------------------------------------------------
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Lback:
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adr r2, Lback
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adr r3, Lforward
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adr r2, Lback
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adr r3, Lforward
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Lforward:
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adr r2, #3
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adr r2, #-3
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adr r2, #3
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adr r2, #-3
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@ CHECK: Lback:
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@ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A]
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@ -145,32 +145,32 @@ Lforward:
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@------------------------------------------------------------------------------
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@ ADD
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@------------------------------------------------------------------------------
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add r4, r5, #0xf000
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add r4, r5, r6
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add r4, r5, r6, lsl #5
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add r4, r5, r6, lsr #5
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add r4, r5, r6, lsr #5
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add r4, r5, r6, asr #5
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add r4, r5, r6, ror #5
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add r6, r7, r8, lsl r9
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add r6, r7, r8, lsr r9
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add r6, r7, r8, asr r9
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add r6, r7, r8, ror r9
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add r4, r5, r6, rrx
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add r4, r5, #0xf000
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add r4, r5, r6
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add r4, r5, r6, lsl #5
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add r4, r5, r6, lsr #5
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add r4, r5, r6, lsr #5
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add r4, r5, r6, asr #5
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add r4, r5, r6, ror #5
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add r6, r7, r8, lsl r9
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add r6, r7, r8, lsr r9
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add r6, r7, r8, asr r9
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add r6, r7, r8, ror r9
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add r4, r5, r6, rrx
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@ destination register is optional
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add r5, #0xf000
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add r4, r5
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add r4, r5, lsl #5
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add r4, r5, lsr #5
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add r4, r5, lsr #5
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add r4, r5, asr #5
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add r4, r5, ror #5
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add r6, r7, lsl r9
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add r6, r7, lsr r9
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add r6, r7, asr r9
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add r6, r7, ror r9
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add r4, r5, rrx
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@ destination register is optional
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add r5, #0xf000
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add r4, r5
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add r4, r5, lsl #5
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add r4, r5, lsr #5
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add r4, r5, lsr #5
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add r4, r5, asr #5
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add r4, r5, ror #5
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add r6, r7, lsl r9
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add r6, r7, lsr r9
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add r6, r7, asr r9
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add r6, r7, ror r9
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add r4, r5, rrx
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@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
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@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
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@ -203,32 +203,32 @@ Lforward:
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@------------------------------------------------------------------------------
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@ AND
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@------------------------------------------------------------------------------
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and r10, r1, #0xf
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and r10, r1, r6
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and r10, r1, r6, lsl #10
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and r10, r1, r6, lsr #10
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and r10, r1, r6, lsr #10
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and r10, r1, r6, asr #10
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and r10, r1, r6, ror #10
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and r6, r7, r8, lsl r2
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and r6, r7, r8, lsr r2
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and r6, r7, r8, asr r2
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and r6, r7, r8, ror r2
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and r10, r1, r6, rrx
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and r10, r1, #0xf
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and r10, r1, r6
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and r10, r1, r6, lsl #10
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and r10, r1, r6, lsr #10
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and r10, r1, r6, lsr #10
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and r10, r1, r6, asr #10
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and r10, r1, r6, ror #10
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and r6, r7, r8, lsl r2
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and r6, r7, r8, lsr r2
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and r6, r7, r8, asr r2
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and r6, r7, r8, ror r2
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and r10, r1, r6, rrx
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@ destination register is optional
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and r1, #0xf
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and r10, r1
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and r10, r1, lsl #10
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and r10, r1, lsr #10
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and r10, r1, lsr #10
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and r10, r1, asr #10
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and r10, r1, ror #10
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and r6, r7, lsl r2
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and r6, r7, lsr r2
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and r6, r7, asr r2
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and r6, r7, ror r2
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and r10, r1, rrx
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@ destination register is optional
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and r1, #0xf
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and r10, r1
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and r10, r1, lsl #10
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and r10, r1, lsr #10
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and r10, r1, lsr #10
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and r10, r1, asr #10
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and r10, r1, ror #10
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and r6, r7, lsl r2
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and r6, r7, lsr r2
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and r6, r7, asr r2
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and r6, r7, ror r2
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and r10, r1, rrx
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@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
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@ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
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@ -266,16 +266,16 @@ Lforward:
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beq _baz
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@ CHECK: b _bar @ encoding: [A,A,A,0xea]
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@ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
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@ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
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@ CHECK: beq _baz @ encoding: [A,A,A,0x0a]
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@ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
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@ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
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@------------------------------------------------------------------------------
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@ BFC
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@------------------------------------------------------------------------------
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bfc r5, #3, #17
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bfccc r5, #3, #17
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bfc r5, #3, #17
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bfccc r5, #3, #17
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@ CHECK: bfc r5, #3, #17 @ encoding: [0x9f,0x51,0xd3,0xe7]
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@ CHECK: bfclo r5, #3, #17 @ encoding: [0x9f,0x51,0xd3,0x37]
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@ -284,8 +284,8 @@ Lforward:
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@------------------------------------------------------------------------------
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@ BFI
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@------------------------------------------------------------------------------
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bfi r5, r2, #3, #17
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bfine r5, r2, #3, #17
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bfi r5, r2, #3, #17
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bfine r5, r2, #3, #17
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@ CHECK: bfi r5, r2, #3, #17 @ encoding: [0x92,0x51,0xd3,0xe7]
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@ CHECK: bfine r5, r2, #3, #17 @ encoding: [0x92,0x51,0xd3,0x17]
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@ -294,32 +294,32 @@ Lforward:
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@------------------------------------------------------------------------------
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@ BIC
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@------------------------------------------------------------------------------
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bic r10, r1, #0xf
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bic r10, r1, r6
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bic r10, r1, r6, lsl #10
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bic r10, r1, r6, lsr #10
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bic r10, r1, r6, lsr #10
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bic r10, r1, r6, asr #10
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bic r10, r1, r6, ror #10
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bic r6, r7, r8, lsl r2
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bic r6, r7, r8, lsr r2
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bic r6, r7, r8, asr r2
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bic r6, r7, r8, ror r2
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bic r10, r1, r6, rrx
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bic r10, r1, #0xf
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bic r10, r1, r6
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bic r10, r1, r6, lsl #10
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bic r10, r1, r6, lsr #10
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bic r10, r1, r6, lsr #10
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bic r10, r1, r6, asr #10
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bic r10, r1, r6, ror #10
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bic r6, r7, r8, lsl r2
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bic r6, r7, r8, lsr r2
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bic r6, r7, r8, asr r2
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bic r6, r7, r8, ror r2
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bic r10, r1, r6, rrx
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@ destination register is optional
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bic r1, #0xf
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bic r10, r1
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bic r10, r1, lsl #10
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bic r10, r1, lsr #10
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bic r10, r1, lsr #10
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bic r10, r1, asr #10
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bic r10, r1, ror #10
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bic r6, r7, lsl r2
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bic r6, r7, lsr r2
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bic r6, r7, asr r2
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bic r6, r7, ror r2
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bic r10, r1, rrx
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@ destination register is optional
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bic r1, #0xf
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bic r10, r1
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bic r10, r1, lsl #10
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bic r10, r1, lsr #10
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bic r10, r1, lsr #10
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bic r10, r1, asr #10
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bic r10, r1, ror #10
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bic r6, r7, lsl r2
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bic r6, r7, lsr r2
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bic r6, r7, asr r2
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bic r6, r7, ror r2
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bic r10, r1, rrx
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@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
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@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
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@ -351,8 +351,8 @@ Lforward:
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@------------------------------------------------------------------------------
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@ BKPT
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@------------------------------------------------------------------------------
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bkpt #10
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bkpt #65535
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bkpt #10
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bkpt #65535
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@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
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@ CHECK: bkpt #65535 @ encoding: [0x7f,0xff,0x2f,0xe1]
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@ -361,11 +361,11 @@ Lforward:
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@ BL/BLX (immediate)
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@------------------------------------------------------------------------------
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bl _bar
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blx _bar
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blls #28634268
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blx #32424576
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blx #16212288
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bl _bar
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blx _bar
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blls #28634268
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blx #32424576
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blx #16212288
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@ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
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@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
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@ -377,8 +377,8 @@ Lforward:
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@------------------------------------------------------------------------------
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@ BLX (register)
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@------------------------------------------------------------------------------
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blx r2
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blxne r2
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blx r2
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blxne r2
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@ CHECK: blx r2 @ encoding: [0x32,0xff,0x2f,0xe1]
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@ CHECK: blxne r2 @ encoding: [0x32,0xff,0x2f,0x11]
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@ -386,9 +386,8 @@ Lforward:
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@------------------------------------------------------------------------------
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@ BX
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@------------------------------------------------------------------------------
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bx r2
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bxne r2
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bx r2
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bxne r2
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@ CHECK: bx r2 @ encoding: [0x12,0xff,0x2f,0xe1]
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@ CHECK: bxne r2 @ encoding: [0x12,0xff,0x2f,0x11]
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@ -396,9 +395,8 @@ Lforward:
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@------------------------------------------------------------------------------
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@ BXJ
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@------------------------------------------------------------------------------
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bxj r2
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bxjne r2
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bxj r2
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bxjne r2
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@ CHECK: bxj r2 @ encoding: [0x22,0xff,0x2f,0xe1]
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@ CHECK: bxjne r2 @ encoding: [0x22,0xff,0x2f,0x11]
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@ -407,8 +405,8 @@ Lforward:
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@------------------------------------------------------------------------------
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@ CDP/CDP2
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@------------------------------------------------------------------------------
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cdp p7, #1, c1, c1, c1, #4
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cdp2 p7, #1, c1, c1, c1, #4
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cdp p7, #1, c1, c1, c1, #4
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cdp2 p7, #1, c1, c1, c1, #4
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|
||||
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
|
||||
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
|
||||
@ -417,7 +415,7 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ CLREX
|
||||
@------------------------------------------------------------------------------
|
||||
clrex
|
||||
clrex
|
||||
|
||||
@ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5]
|
||||
|
||||
@ -425,8 +423,8 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ CLZ
|
||||
@------------------------------------------------------------------------------
|
||||
clz r1, r2
|
||||
clzeq r1, r2
|
||||
clz r1, r2
|
||||
clzeq r1, r2
|
||||
|
||||
@ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1]
|
||||
@ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01]
|
||||
@ -434,18 +432,18 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ CMN
|
||||
@------------------------------------------------------------------------------
|
||||
cmn r1, #0xf
|
||||
cmn r1, r6
|
||||
cmn r1, r6, lsl #10
|
||||
cmn r1, r6, lsr #10
|
||||
cmn sp, r6, lsr #10
|
||||
cmn r1, r6, asr #10
|
||||
cmn r1, r6, ror #10
|
||||
cmn r7, r8, lsl r2
|
||||
cmn sp, r8, lsr r2
|
||||
cmn r7, r8, asr r2
|
||||
cmn r7, r8, ror r2
|
||||
cmn r1, r6, rrx
|
||||
cmn r1, #0xf
|
||||
cmn r1, r6
|
||||
cmn r1, r6, lsl #10
|
||||
cmn r1, r6, lsr #10
|
||||
cmn sp, r6, lsr #10
|
||||
cmn r1, r6, asr #10
|
||||
cmn r1, r6, ror #10
|
||||
cmn r7, r8, lsl r2
|
||||
cmn sp, r8, lsr r2
|
||||
cmn r7, r8, asr r2
|
||||
cmn r7, r8, ror r2
|
||||
cmn r1, r6, rrx
|
||||
|
||||
@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
|
||||
@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
|
||||
@ -463,18 +461,18 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ CMP
|
||||
@------------------------------------------------------------------------------
|
||||
cmp r1, #0xf
|
||||
cmp r1, r6
|
||||
cmp r1, r6, lsl #10
|
||||
cmp r1, r6, lsr #10
|
||||
cmp sp, r6, lsr #10
|
||||
cmp r1, r6, asr #10
|
||||
cmp r1, r6, ror #10
|
||||
cmp r7, r8, lsl r2
|
||||
cmp sp, r8, lsr r2
|
||||
cmp r7, r8, asr r2
|
||||
cmp r7, r8, ror r2
|
||||
cmp r1, r6, rrx
|
||||
cmp r1, #0xf
|
||||
cmp r1, r6
|
||||
cmp r1, r6, lsl #10
|
||||
cmp r1, r6, lsr #10
|
||||
cmp sp, r6, lsr #10
|
||||
cmp r1, r6, asr #10
|
||||
cmp r1, r6, ror #10
|
||||
cmp r7, r8, lsl r2
|
||||
cmp sp, r8, lsr r2
|
||||
cmp r7, r8, asr r2
|
||||
cmp r7, r8, ror r2
|
||||
cmp r1, r6, rrx
|
||||
|
||||
@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
|
||||
@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
|
||||
@ -505,9 +503,9 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ DBG
|
||||
@------------------------------------------------------------------------------
|
||||
dbg #0
|
||||
dbg #5
|
||||
dbg #15
|
||||
dbg #0
|
||||
dbg #5
|
||||
dbg #15
|
||||
|
||||
@ CHECK: dbg #0 @ encoding: [0xf0,0xf0,0x20,0xe3]
|
||||
@ CHECK: dbg #5 @ encoding: [0xf5,0xf0,0x20,0xe3]
|
||||
@ -517,19 +515,19 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ DMB
|
||||
@------------------------------------------------------------------------------
|
||||
dmb sy
|
||||
dmb st
|
||||
dmb sh
|
||||
dmb ish
|
||||
dmb shst
|
||||
dmb ishst
|
||||
dmb un
|
||||
dmb nsh
|
||||
dmb unst
|
||||
dmb nshst
|
||||
dmb osh
|
||||
dmb oshst
|
||||
dmb
|
||||
dmb sy
|
||||
dmb st
|
||||
dmb sh
|
||||
dmb ish
|
||||
dmb shst
|
||||
dmb ishst
|
||||
dmb un
|
||||
dmb nsh
|
||||
dmb unst
|
||||
dmb nshst
|
||||
dmb osh
|
||||
dmb oshst
|
||||
dmb
|
||||
|
||||
@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5]
|
||||
@ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5]
|
||||
@ -548,19 +546,19 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ DSB
|
||||
@------------------------------------------------------------------------------
|
||||
dsb sy
|
||||
dsb st
|
||||
dsb sh
|
||||
dsb ish
|
||||
dsb shst
|
||||
dsb ishst
|
||||
dsb un
|
||||
dsb nsh
|
||||
dsb unst
|
||||
dsb nshst
|
||||
dsb osh
|
||||
dsb oshst
|
||||
dsb
|
||||
dsb sy
|
||||
dsb st
|
||||
dsb sh
|
||||
dsb ish
|
||||
dsb shst
|
||||
dsb ishst
|
||||
dsb un
|
||||
dsb nsh
|
||||
dsb unst
|
||||
dsb nshst
|
||||
dsb osh
|
||||
dsb oshst
|
||||
dsb
|
||||
|
||||
@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5]
|
||||
@ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5]
|
||||
@ -579,32 +577,32 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ EOR
|
||||
@------------------------------------------------------------------------------
|
||||
eor r4, r5, #0xf000
|
||||
eor r4, r5, r6
|
||||
eor r4, r5, r6, lsl #5
|
||||
eor r4, r5, r6, lsr #5
|
||||
eor r4, r5, r6, lsr #5
|
||||
eor r4, r5, r6, asr #5
|
||||
eor r4, r5, r6, ror #5
|
||||
eor r6, r7, r8, lsl r9
|
||||
eor r6, r7, r8, lsr r9
|
||||
eor r6, r7, r8, asr r9
|
||||
eor r6, r7, r8, ror r9
|
||||
eor r4, r5, r6, rrx
|
||||
eor r4, r5, #0xf000
|
||||
eor r4, r5, r6
|
||||
eor r4, r5, r6, lsl #5
|
||||
eor r4, r5, r6, lsr #5
|
||||
eor r4, r5, r6, lsr #5
|
||||
eor r4, r5, r6, asr #5
|
||||
eor r4, r5, r6, ror #5
|
||||
eor r6, r7, r8, lsl r9
|
||||
eor r6, r7, r8, lsr r9
|
||||
eor r6, r7, r8, asr r9
|
||||
eor r6, r7, r8, ror r9
|
||||
eor r4, r5, r6, rrx
|
||||
|
||||
@ destination register is optional
|
||||
eor r5, #0xf000
|
||||
eor r4, r5
|
||||
eor r4, r5, lsl #5
|
||||
eor r4, r5, lsr #5
|
||||
eor r4, r5, lsr #5
|
||||
eor r4, r5, asr #5
|
||||
eor r4, r5, ror #5
|
||||
eor r6, r7, lsl r9
|
||||
eor r6, r7, lsr r9
|
||||
eor r6, r7, asr r9
|
||||
eor r6, r7, ror r9
|
||||
eor r4, r5, rrx
|
||||
@ destination register is optional
|
||||
eor r5, #0xf000
|
||||
eor r4, r5
|
||||
eor r4, r5, lsl #5
|
||||
eor r4, r5, lsr #5
|
||||
eor r4, r5, lsr #5
|
||||
eor r4, r5, asr #5
|
||||
eor r4, r5, ror #5
|
||||
eor r6, r7, lsl r9
|
||||
eor r6, r7, lsr r9
|
||||
eor r6, r7, asr r9
|
||||
eor r6, r7, ror r9
|
||||
eor r4, r5, rrx
|
||||
|
||||
@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2]
|
||||
@ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0]
|
||||
@ -693,8 +691,8 @@ Lforward:
|
||||
ldrhthi r8, [r11], #-0
|
||||
ldrhthi r8, [r11], #0
|
||||
|
||||
@ CHECK: ldrhthi r8, [r11], #-0 @ encoding: [0xb0,0x80,0x7b,0x80]
|
||||
@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80]
|
||||
@ CHECK: ldrhthi r8, [r11], #-0 @ encoding: [0xb0,0x80,0x7b,0x80]
|
||||
@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80]
|
||||
|
||||
@------------------------------------------------------------------------------
|
||||
@ FIXME: LSL
|
||||
@ -747,14 +745,14 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ MOV (immediate)
|
||||
@------------------------------------------------------------------------------
|
||||
mov r3, #7
|
||||
mov r4, #0xff0
|
||||
mov r5, #0xff0000
|
||||
mov r6, #0xffff
|
||||
movw r9, #0xffff
|
||||
movs r3, #7
|
||||
moveq r4, #0xff0
|
||||
movseq r5, #0xff0000
|
||||
mov r3, #7
|
||||
mov r4, #0xff0
|
||||
mov r5, #0xff0000
|
||||
mov r6, #0xffff
|
||||
movw r9, #0xffff
|
||||
movs r3, #7
|
||||
moveq r4, #0xff0
|
||||
movseq r5, #0xff0000
|
||||
|
||||
@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3]
|
||||
@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3]
|
||||
@ -781,9 +779,9 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ MOVT
|
||||
@------------------------------------------------------------------------------
|
||||
movt r3, #7
|
||||
movt r6, #0xffff
|
||||
movteq r4, #0xff0
|
||||
movt r3, #7
|
||||
movt r6, #0xffff
|
||||
movteq r4, #0xff0
|
||||
|
||||
@ CHECK: movt r3, #7 @ encoding: [0x07,0x30,0x40,0xe3]
|
||||
@ CHECK: movt r6, #65535 @ encoding: [0xff,0x6f,0x4f,0xe3]
|
||||
@ -888,11 +886,10 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ MUL
|
||||
@------------------------------------------------------------------------------
|
||||
|
||||
mul r5, r6, r7
|
||||
muls r5, r6, r7
|
||||
mulgt r5, r6, r7
|
||||
mulsle r5, r6, r7
|
||||
mul r5, r6, r7
|
||||
muls r5, r6, r7
|
||||
mulgt r5, r6, r7
|
||||
mulsle r5, r6, r7
|
||||
|
||||
@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0]
|
||||
@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
|
||||
@ -903,12 +900,12 @@ Lforward:
|
||||
@------------------------------------------------------------------------------
|
||||
@ MVN (immediate)
|
||||
@------------------------------------------------------------------------------
|
||||
mvn r3, #7
|
||||
mvn r4, #0xff0
|
||||
mvn r5, #0xff0000
|
||||
mvns r3, #7
|
||||
mvneq r4, #0xff0
|
||||
mvnseq r5, #0xff0000
|
||||
mvn r3, #7
|
||||
mvn r4, #0xff0
|
||||
mvn r5, #0xff0000
|
||||
mvns r3, #7
|
||||
mvneq r4, #0xff0
|
||||
mvnseq r5, #0xff0000
|
||||
|
||||
@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3]
|
||||
@ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user