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ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -365,10 +365,10 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
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/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CSPR register.
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let Defs = [CPSR] in {
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multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
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multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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opc, "s $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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@ -430,18 +430,18 @@ multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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Requires<[IsARM, HasV6]>;
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}
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/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
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/// setting carry bit. But it can optionally set CPSR.
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let Uses = [CPSR] in {
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multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
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DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
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/// AI1_bin_cs_irs - A binary operation that both uses and defines CPSR. It's
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/// currently not predicable.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass AI1_bin_cs_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, !strconcat(opc, "s $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
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DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
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def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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DPFrm, !strconcat(opc, "s $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
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DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"),
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def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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}
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@ -905,16 +905,16 @@ defm SUB : AsI1_bin_irs<0b0010, "sub",
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BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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// ADD and SUB with 's' bit set.
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defm ADDS : ASI1_bin_s_irs<0b0100, "add",
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BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm SUBS : ASI1_bin_s_irs<0b0010, "sub",
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BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm ADDS : AI1_bin_s_irs<0b0100, "add",
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BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm SUBS : AI1_bin_s_irs<0b0010, "sub",
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BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// FIXME: Do not allow ADC / SBC to be predicated for now.
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defm ADC : AsXI1_bin_c_irs<0b0101, "adc",
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BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm SBC : AsXI1_bin_c_irs<0b0110, "sbc",
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BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// FIXME: Do not allow ADCS / SBCS to be predicated for now.
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defm ADCS : AI1_bin_cs_irs<0b0101, "adc",
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BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm SBCS : AI1_bin_cs_irs<0b0110, "sbc",
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BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// These don't define reg/reg forms, because they are handled above.
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def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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@ -935,14 +935,14 @@ def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
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}
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// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
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let Uses = [CPSR] in {
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def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
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DPFrm, "rsc${s} $dst, $a, $b",
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[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
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def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
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DPSoRegFrm, "rsc${s} $dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
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// FIXME: Do not allow RSC to be predicated for now.
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let Defs = [CPSR], Uses = [CPSR] in {
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def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, "rscs $dst, $a, $b",
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[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
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def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, "rscs $dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
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}
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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@ -169,16 +169,14 @@ multiclass T2I_bin_irs<string opc, PatFrag opnode> {
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_rbin_irs - Same as T2I_bin_irs except the order of operands are reversed.
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multiclass T2I_rbin_irs<string opc, PatFrag opnode> {
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/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_bin_irs counterpart.
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multiclass T2I_rbin_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// register
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def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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opc, " $dst, $rhs, $lhs",
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@ -204,25 +202,6 @@ multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
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}
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}
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/// T2I_rbin_s_irs - Same as T2I_bin_s_irs except the order of operands are
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/// reversed.
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let Defs = [CPSR] in {
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multiclass T2I_rbin_s_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, "s"), " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// register
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def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
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!strconcat(opc, "s"), " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, "s"), " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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}
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/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
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/// patterns for a binary operation that produces a value.
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multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
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@ -244,38 +223,55 @@ multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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// binary operation that produces a value and set the carry bit. It can also
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/// optionally set CPSR.
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let Uses = [CPSR] in {
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multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
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/// T2I_bin_cs_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// binary operation that produces a value and use and define the carry bit.
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/// It's not predicable.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass T2I_bin_cs_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// register
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def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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}
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/// T2I_rbin_c_irs - Same as T2I_bin_c_irs except the order of operands are
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/// reversed.
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let Uses = [CPSR] in {
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multiclass T2I_rbin_c_irs<string opc, PatFrag opnode> {
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/// T2I_rbin_cs_is - Same as T2I_bin_cs_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_bin_cs_irs counterpart.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass T2I_rbin_cs_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// register
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def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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}
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/// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_bin_s_irs counterpart.
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let Defs = [CPSR] in {
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multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// register
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def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $rhs, $lhs"),
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@ -386,17 +382,17 @@ defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
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defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
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defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// FIXME: predication support
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defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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defm t2ADC : T2I_bin_cs_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_bin_cs_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// RSB, RSC
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defm t2RSB : T2I_rbin_irs <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm t2RSBS : T2I_rbin_c_irs<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2RSC : T2I_rbin_s_irs<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2RSC : T2I_rbin_cs_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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16
test/CodeGen/ARM/carry.ll
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16
test/CodeGen/ARM/carry.ll
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@ -0,0 +1,16 @@
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; RUN: llvm-as < %s | llc -march=arm | grep "subs r" | count 2
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; RUN: llvm-as < %s | llc -march=arm | grep adc
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; RUN: llvm-as < %s | llc -march=arm | grep sbc
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define i64 @f1(i64 %a, i64 %b) {
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entry:
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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entry:
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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16
test/CodeGen/Thumb2/carry.ll
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16
test/CodeGen/Thumb2/carry.ll
Normal file
@ -0,0 +1,16 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "subs r" | count 2
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep adc
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep sbc
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define i64 @f1(i64 %a, i64 %b) {
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entry:
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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entry:
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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