6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-15 04:08:07 +00:00
Code Issues Projects Releases Wiki Activity

Simplify SplitVecRes_EXTRACT_SUBVECTOR. This means

Browse Source 
that it no longer handles non-power-of-two vectors.
However it previously only handled them sometimes,
depending on obscure numerical relationships between
the index and vector type.  For example, for a vector
of length 6, it would succeed if and only if the
index was an even multiple of 6.  I consider this
more confusing than useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59122 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-11-12 08:37:57 +00:00
parent 245146b58a
commit 1e465a35c8
1 changed files with 13 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -355,8 +355,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
case ISD::CTTZ:
case ISD::CTLZ:
@ -520,28 +520,20 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
MVT IdxVT = Idx.getValueType();
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
MVT IdxVT = Idx.getValueType();
ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
if (CIdx) {
unsigned IdxVal = CIdx->getZExtValue();
assert (IdxVal % LoVT.getVectorNumElements() == 0 &&
(IdxVal+LoNumElts) % HiVT.getVectorNumElements()==0 &&
"Index must be a multiple of the result type");
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec,
DAG.getConstant(IdxVal + LoNumElts, IdxVT));
} else {
assert(LoVT == HiVT && "Low and High value type should be the same");
Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, DAG.getConstant(LoNumElts, IdxVT));
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
}
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// The indices are not guaranteed to be a multiple of the new vector
// size unless the original vector type was split in two.
assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
}
void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,