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Support insertps via the intrinsic and add a couple of simple
testcases to make sure it's being generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3590,15 +3590,19 @@ let Constraints = "$src1 = $dst" in {
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defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
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defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
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// insertps has a few different modes, there's the first two here below which
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// are optimized inserts that won't zero arbitrary elements in the destination
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// vector. The next one matches the intrinsic and could zero arbitrary elements
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// in the target vector.
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
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multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
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def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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def match_rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
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(ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
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(X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
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def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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def match_rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
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(ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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@ -3608,6 +3612,14 @@ let Constraints = "$src1 = $dst" in {
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}
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}
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}
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}
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let Constraints = "$src1 = $dst" in {
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def INSERTPSrr : SS4AIi8<0x21, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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"insertps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (int_x86_sse41_insertps VR128:$src1,
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VR128:$src2, imm:$src3))]>;
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}
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defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
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defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
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let Defs = [EFLAGS] in {
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let Defs = [EFLAGS] in {
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13
test/CodeGen/X86/vec_insertps-1.ll
Normal file
13
test/CodeGen/X86/vec_insertps-1.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep insertps | count 2
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define <4 x float> @t1(<4 x float> %t1, <4 x float> %t2) nounwind {
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%tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
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ret <4 x float> %tmp1
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @t2(<4 x float> %t1, float %t2) nounwind {
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%tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
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ret <4 x float> %tmp1
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}
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