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enhance new encoder to support prefixes + RawFrm

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instructions with no operands.  It can now handle

define void @test2() nounwind { ret void }



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95261 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-02-03 21:57:59 +00:00
parent 92b1dfe5d8
commit 1e80f403e2
3 changed files with 133 additions and 7 deletions
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2
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -559,7 +559,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
--NumOps;
unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(*Desc);
switch (Desc->TSFlags & X86II::FormMask) {
default:
llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");

6
lib/Target/X86/X86InstrInfo.h
View File

@ -640,11 +640,11 @@ public:
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.
//
unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
return TID->TSFlags >> X86II::OpcodeShift;
static unsigned char getBaseOpcodeFor(const TargetInstrDesc &TID) {
return TID.TSFlags >> X86II::OpcodeShift;
}
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
return getBaseOpcodeFor(&get(Opcode));
return getBaseOpcodeFor(get(Opcode));
}
static bool isX86_64NonExtLowByteReg(unsigned reg) {

132
lib/Target/X86/X86MCCodeEmitter.cpp
View File

@ -54,13 +54,17 @@ void X86MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
unsigned Opcode = MI.getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned TSFlags = Desc.TSFlags;
// FIXME: We should emit the prefixes in exactly the same order as GAS does,
// in order to provide diffability.
// Emit the lock opcode prefix as needed.
if (Desc.TSFlags & X86II::LOCK)
if (TSFlags & X86II::LOCK)
EmitByte(0xF0, OS);
// Emit segment override opcode prefix as needed.
switch (Desc.TSFlags & X86II::SegOvrMask) {
switch (TSFlags & X86II::SegOvrMask) {
default: assert(0 && "Invalid segment!");
case 0: break; // No segment override!
case X86II::FS:
@ -71,5 +75,127 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
break;
}
// Emit the repeat opcode prefix as needed.
if ((TSFlags & X86II::Op0Mask) == X86II::REP)
EmitByte(0xF3, OS);
// Emit the operand size opcode prefix as needed.
if (TSFlags & X86II::OpSize)
EmitByte(0x66, OS);
// Emit the address size opcode prefix as needed.
if (TSFlags & X86II::AdSize)
EmitByte(0x67, OS);
bool Need0FPrefix = false;
switch (TSFlags & X86II::Op0Mask) {
default: assert(0 && "Invalid prefix!");
case 0: break; // No prefix!
case X86II::REP: break; // already handled.
case X86II::TB: // Two-byte opcode prefix
case X86II::T8: // 0F 38
case X86II::TA: // 0F 3A
Need0FPrefix = true;
break;
case X86II::TF: // F2 0F 38
EmitByte(0xF2, OS);
Need0FPrefix = true;
break;
case X86II::XS: // F3 0F
EmitByte(0xF3, OS);
Need0FPrefix = true;
break;
case X86II::XD: // F2 0F
EmitByte(0xF2, OS);
Need0FPrefix = true;
break;
case X86II::D8: EmitByte(0xD8, OS); break;
case X86II::D9: EmitByte(0xD9, OS); break;
case X86II::DA: EmitByte(0xDA, OS); break;
case X86II::DB: EmitByte(0xDB, OS); break;
case X86II::DC: EmitByte(0xDC, OS); break;
case X86II::DD: EmitByte(0xDD, OS); break;
case X86II::DE: EmitByte(0xDE, OS); break;
case X86II::DF: EmitByte(0xDF, OS); break;
}
// Handle REX prefix.
#if 0 // FIXME: Add in, also, can this come before F2 etc to simplify emission?
if (Is64BitMode) {
if (unsigned REX = X86InstrInfo::determineREX(MI))
EmitByte(0x40 | REX, OS);
}
#endif
// 0x0F escape code must be emitted just before the opcode.
if (Need0FPrefix)
EmitByte(0x0F, OS);
// FIXME: Pull this up into previous switch if REX can be moved earlier.
switch (TSFlags & X86II::Op0Mask) {
case X86II::TF: // F2 0F 38
case X86II::T8: // 0F 38
EmitByte(0x38, OS);
break;
case X86II::TA: // 0F 3A
EmitByte(0x3A, OS);
break;
}
// If this is a two-address instruction, skip one of the register operands.
unsigned NumOps = Desc.getNumOperands();
unsigned CurOp = 0;
if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
++CurOp;
else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
--NumOps;
unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc);
switch (TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
case X86II::RawFrm: {
EmitByte(BaseOpcode, OS);
if (CurOp == NumOps)
break;
assert(0 && "Unimpl");
#if 0
const MachineOperand &MO = MI.getOperand(CurOp++);
DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
if (MO.isMBB()) {
emitPCRelativeBlockAddress(MO.getMBB());
break;
}
if (MO.isGlobal()) {
emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
MO.getOffset(), 0);
break;
}
if (MO.isSymbol()) {
emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
break;
}
assert(MO.isImm() && "Unknown RawFrm operand!");
if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
// Fix up immediate operand for pc relative calls.
intptr_t Imm = (intptr_t)MO.getImm();
Imm = Imm - MCE.getCurrentPCValue() - 4;
emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
} else
emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
#endif
}
}
}