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[PPC] Implement vmrgew and vmrgow instructions
This patch adds support for the vector merge even word and vector merge odd word instructions introduced in POWER8. Phabricator review: http://reviews.llvm.org/D10704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240650 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kit Barton
parent
39b2e22f00
commit
1ebbc68719
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@ -1279,6 +1279,99 @@ bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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}
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}
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/**
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* \brief Common function used to match vmrgew and vmrgow shuffles
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*
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* The indexOffset determines whether to look for even or odd words in
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* the shuffle mask. This is based on the of the endianness of the target
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* machine.
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* - Little Endian:
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* - Use offset of 0 to check for odd elements
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* - Use offset of 4 to check for even elements
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* - Big Endian:
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* - Use offset of 0 to check for even elements
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* - Use offset of 4 to check for odd elements
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* A detailed description of the vector element ordering for little endian and
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* big endian can be found at <a
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* href="http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html">
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* Targeting your applications - what little endian and big endian IBM XL C/C++
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* compiler differences mean to you </a>
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*
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* The mask to the shuffle vector instruction specifies the indices of the
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* elements from the two input vectors to place in the result. The elements are
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* numbered in array-access order, starting with the first vector. These vectors
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* are always of type v16i8, thus each vector will contain 16 elements of size
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* 8. More info on the shuffle vector can be found in the <a
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* href="http://llvm.org/docs/LangRef.html#shufflevector-instruction">Language
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* Reference</a>.
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*
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* The RHSStartValue indicates whether the same input vectors are used (unary)
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* or two different input vectors are used, based on the following:
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* - If the instruction uses the same vector for both inputs, the range of the
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* indices will be 0 to 15. In this case, the RHSStart value passed should
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* be 0.
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* - If the instruction has two different vectors then the range of the
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* indices will be 0 to 31. In this case, the RHSStart value passed should
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* be 16 (indices 0-15 specify elements in the first vector while indices 16
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* to 31 specify elements in the second vector).
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*
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* \param[in] N The shuffle vector SD Node to analyze
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* \param[in] IndexOffset Specifies whether to look for even or odd elements
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* \param[in] RHSStartValue Specifies the starting index for the righthand input
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* vector to the shuffle_vector instruction
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* \return true iff this shuffle vector represents an even or odd word merge
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*/
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static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
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unsigned RHSStartValue) {
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if (N->getValueType(0) != MVT::v16i8)
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return false;
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for (unsigned i = 0; i < 2; ++i)
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for (unsigned j = 0; j < 4; ++j)
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if (!isConstantOrUndef(N->getMaskElt(i*4+j),
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i*RHSStartValue+j+IndexOffset) ||
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!isConstantOrUndef(N->getMaskElt(i*4+j+8),
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i*RHSStartValue+j+IndexOffset+8))
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return false;
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return true;
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}
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/**
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* \brief Determine if the specified shuffle mask is suitable for the vmrgew or
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* vmrgow instructions.
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*
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* \param[in] N The shuffle vector SD Node to analyze
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* \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
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* \param[in] ShuffleKind Identify the type of merge:
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* - 0 = big-endian merge with two different inputs;
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* - 1 = either-endian merge with two identical inputs;
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* - 2 = little-endian merge with two different inputs (inputs are swapped for
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* little-endian merges).
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* \param[in] DAG The current SelectionDAG
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* \return true iff this shuffle mask
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*/
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bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
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unsigned ShuffleKind, SelectionDAG &DAG) {
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if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
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unsigned indexOffset = CheckEven ? 4 : 0;
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if (ShuffleKind == 1) // Unary
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return isVMerge(N, indexOffset, 0);
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else if (ShuffleKind == 2) // swapped
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return isVMerge(N, indexOffset, 16);
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else
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return false;
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}
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else {
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unsigned indexOffset = CheckEven ? 0 : 4;
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if (ShuffleKind == 1) // Unary
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return isVMerge(N, indexOffset, 0);
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else if (ShuffleKind == 0) // Normal
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return isVMerge(N, indexOffset, 16);
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else
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return false;
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}
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return false;
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}
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
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/// amount, otherwise return -1.
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@ -7046,7 +7139,9 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
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PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
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PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
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PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
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return Op;
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}
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}
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@ -7064,7 +7159,9 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
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PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
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PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
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PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
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return Op;
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// Check to see if this is a shuffle of 4-byte values. If so, we can use our
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@ -382,6 +382,11 @@ namespace llvm {
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bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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unsigned ShuffleKind, SelectionDAG &DAG);
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/// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VMRGEW or VMRGOW instruction
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bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
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unsigned ShuffleKind, SelectionDAG &DAG);
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
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/// shift amount, otherwise return -1.
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int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
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@ -155,6 +155,33 @@ def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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}]>;
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def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG);
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}]>;
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def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG);
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}]>;
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def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG);
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}]>;
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def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG);
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}]>;
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def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG);
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}]>;
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def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG);
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}]>;
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def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
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return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N));
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}]>;
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@ -1008,6 +1035,29 @@ def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
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def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
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} // isCommutable
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// Vector merge
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def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmrgew $vD, $vA, $vB", IIC_VecFP,
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[(set v16i8:$vD, (vmrgew_shuffle v16i8:$vA, v16i8:$vB))]>;
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def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmrgow $vD, $vA, $vB", IIC_VecFP,
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[(set v16i8:$vD, (vmrgow_shuffle v16i8:$vA, v16i8:$vB))]>;
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// Match vmrgew(x,x) and vmrgow(x,x)
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def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef),
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(VMRGEW $vA, $vA)>;
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def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef),
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(VMRGOW $vA, $vA)>;
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// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments
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// are matched for little-endian, where the inputs must be swapped for correct
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// semantics.w
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def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB),
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(VMRGEW $vB, $vA)>;
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def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB),
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(VMRGOW $vB, $vA)>;
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// Vector shifts
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def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
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def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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101
test/CodeGen/PowerPC/vec_mergeow.ll
Normal file
101
test/CodeGen/PowerPC/vec_mergeow.ll
Normal file
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@ -0,0 +1,101 @@
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-LE
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-BE
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; Check for a vector merge instruction using two inputs
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; The shufflevector specifies the even elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgew
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; instruction. If run on a little endian machine, this should produce the
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; vmrgow instruction. Note also that on little endian the input registers
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; are swapped also.
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define void @check_merge_even_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK-LE-LABEL: @check_merge_even_xy
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; CHECK-BE-LABEL: @check_merge_even_xy
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 16, i32 17, i32 18, i32 19,
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i32 8, i32 9, i32 10, i32 11,
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i32 24, i32 25, i32 26, i32 27>
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; CHECK-LE: vmrgow 2, 3, 2
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; CHECK-BE: vmrgew 2, 2, 3
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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; Check for a vector merge instruction using a single input.
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; The shufflevector specifies the even elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgew
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; instruction. If run on a little endian machine, this should produce the
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; vmrgow instruction.
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define void @check_merge_even_xx(<16 x i8>* %A) {
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entry:
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; CHECK-LE-LABEL: @check_merge_even_xx
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; CHECK-BE-LABEL: @check_merge_even_xx
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 0, i32 1, i32 2, i32 3,
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i32 8, i32 9, i32 10, i32 11,
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i32 8, i32 9, i32 10, i32 11>
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; CHECK-LE: vmrgow 2, 2, 2
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; CHECK-BE: vmrgew 2, 2, 2
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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; Check for a vector merge instruction using two inputs.
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; The shufflevector specifies the odd elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgow
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; instruction. If run on a little endian machine, this should produce the
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; vmrgew instruction. Note also that on little endian the input registers
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; are swapped also.
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define void @check_merge_odd_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK-LE-LABEL: @check_merge_odd_xy
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; CHECK-BE-LABEL: @check_merge_odd_xy
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2,
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<16 x i32> <i32 4, i32 5, i32 6, i32 7,
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i32 20, i32 21, i32 22, i32 23,
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i32 12, i32 13, i32 14, i32 15,
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i32 28, i32 29, i32 30, i32 31>
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; CHECK-LE: vmrgew 2, 3, 2
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; CHECK-BE: vmrgow 2, 2, 3
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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; Check for a vector merge instruction using a single input.
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; The shufflevector specifies the odd elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgow
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; instruction. If run on a little endian machine, this should produce the
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; vmrgew instruction.
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define void @check_merge_odd_xx(<16 x i8>* %A) {
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entry:
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; CHECK-LE-LABEL: @check_merge_odd_xx
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; CHECK-BE-LABEL: @check_merge_odd_xx
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp,
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<16 x i32> <i32 4, i32 5, i32 6, i32 7,
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i32 4, i32 5, i32 6, i32 7,
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i32 12, i32 13, i32 14, i32 15,
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i32 12, i32 13, i32 14, i32 15>
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; CHECK-LE: vmrgew 2, 2, 2
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; CHECK-BE: vmrgow 2, 2, 2
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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@ -99,6 +99,12 @@
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# CHECK: vmrglw 2, 3, 4
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0x10 0x43 0x21 0x8c
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# CHECK: vmrgew 2, 3, 4
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0x10 0x43 0x27 0x8c
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# CHECK: vmrgow 2, 3, 4
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0x10 0x43 0x26 0x8c
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# CHECK: vspltb 2, 3, 1
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0x10 0x41 0x1a 0x0c
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@ -1,5 +1,5 @@
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
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# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
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# Vector facility
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@ -110,7 +110,13 @@
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# CHECK-BE: vmrglw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8c]
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# CHECK-LE: vmrglw 2, 3, 4 # encoding: [0x8c,0x21,0x43,0x10]
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vmrglw 2, 3, 4
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# CHECK-BE: vmrgew 2, 3, 4 # encoding: [0x10,0x43,0x27,0x8c]
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# CHECK-LE: vmrgew 2, 3, 4 # encoding: [0x8c,0x27,0x43,0x10]
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vmrgew 2, 3, 4
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# CHECK-BE: vmrgow 2, 3, 4 # encoding: [0x10,0x43,0x26,0x8c]
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# CHECK-LE: vmrgow 2, 3, 4 # encoding: [0x8c,0x26,0x43,0x10]
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vmrgow 2, 3, 4
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# CHECK-BE: vspltb 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x0c]
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# CHECK-LE: vspltb 2, 3, 1 # encoding: [0x0c,0x1a,0x41,0x10]
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vspltb 2, 3, 1
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