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[mips] 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -96,7 +96,8 @@ private:
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unsigned Reg1, unsigned Reg2) const;
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -22,7 +22,8 @@ class Mips16InstrInfo;
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class Mips16RegisterInfo : public MipsRegisterInfo {
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const Mips16InstrInfo &TII;
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public:
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Mips16RegisterInfo(const MipsSubtarget &Subtarget, const Mips16InstrInfo &TII);
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Mips16RegisterInfo(const MipsSubtarget &Subtarget,
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const Mips16InstrInfo &TII);
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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@ -330,8 +330,12 @@ def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc0 $rt, $rd",
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(DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc0 $rt, $rd",
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(DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc2 $rt, $rd",
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(DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc2 $rt, $rd",
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(DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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