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ARM parsing aliases for data-size suffices on VST1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145454 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-29 23:21:31 +00:00
parent 7c6b2c9a70
commit 1ec7bf0c0d
1 changed files with 56 additions and 19 deletions
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75
lib/Target/ARM/ARMInstrNEON.td
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@ -5448,28 +5448,65 @@ defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1q64wb_register zero_reg, addrmode6:$Rn,
rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
// FIXME: The three and four register VST1 instructions haven't been moved
// to the VecList* encoding yet, so we can't do assembly parsing support
// for them. Uncomment these when that happens.
// Load three D registers.
//defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
//defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
//defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d8Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d16Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d32Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d64Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d8Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d16Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d32Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListThreeD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d64Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListThreeD:$Vd, pred:$p)>;
// Load four D registers.
//defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d8Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d16Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d32Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
(VST1d64Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d8Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListFourD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d16Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListFourD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d32Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListFourD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
(VST1d64Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
VecListFourD:$Vd, pred:$p)>;
// VTRN instructions data type suffix aliases for more-specific types.