diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d3df3dc316a..e2df2ab16c0 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -227,6 +227,7 @@ class ARMAsmParser : public MCTargetAsmParser {
   bool parseDirectiveTLSDescSeq(SMLoc L);
   bool parseDirectiveMovSP(SMLoc L);
   bool parseDirectiveObjectArch(SMLoc L);
+  bool parseDirectiveArchExtension(SMLoc L);
 
   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
                           bool &CarrySetting, unsigned &ProcessorIMod,
@@ -8016,6 +8017,8 @@ bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
     return parseDirectiveMovSP(DirectiveID.getLoc());
   else if (IDVal == ".object_arch")
     return parseDirectiveObjectArch(DirectiveID.getLoc());
+  else if (IDVal == ".arch_extension")
+    return parseDirectiveArchExtension(DirectiveID.getLoc());
   return true;
 }
 
@@ -9064,6 +9067,85 @@ extern "C" void LLVMInitializeARMAsmParser() {
 #define GET_MATCHER_IMPLEMENTATION
 #include "ARMGenAsmMatcher.inc"
 
+static const struct ExtMapEntry {
+  const char *Extension;
+  const unsigned ArchCheck;
+  const uint64_t Features;
+} Extensions[] = {
+  { "crc", Feature_HasV8, ARM::FeatureCRC },
+  { "crypto",  Feature_HasV8,
+    ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
+  { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
+  { "idiv", Feature_HasV7 | Feature_IsNotMClass,
+    ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
+  // FIXME: iWMMXT not supported
+  { "iwmmxt", Feature_None, 0 },
+  // FIXME: iWMMXT2 not supported
+  { "iwmmxt2", Feature_None, 0 },
+  // FIXME: Maverick not supported
+  { "maverick", Feature_None, 0 },
+  { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
+  // FIXME: ARMv6-m OS Extensions feature not checked
+  { "os", Feature_None, 0 },
+  // FIXME: Also available in ARMv6-K
+  { "sec", Feature_HasV7, ARM::FeatureTrustZone },
+  { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
+  // FIXME: Only available in A-class, isel not predicated
+  { "virt", Feature_HasV7, ARM::FeatureVirtualization },
+  // FIXME: xscale not supported
+  { "xscale", Feature_None, 0 },
+};
+
+template <typename T, size_t N>
+size_t countof(const T (&)[N]) { return N; }
+
+/// parseDirectiveArchExtension
+///   ::= .arch_extension [no]feature
+bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
+  if (getLexer().isNot(AsmToken::Identifier)) {
+    Error(getLexer().getLoc(), "unexpected token");
+    Parser.eatToEndOfStatement();
+    return false;
+  }
+
+  StringRef Extension = Parser.getTok().getString();
+  SMLoc ExtLoc = Parser.getTok().getLoc();
+  getLexer().Lex();
+
+  bool EnableFeature = true;
+  if (!Extension.lower().compare(0, 2, "no")) {
+    EnableFeature = false;
+    Extension = Extension.substr(2);
+  }
+
+  for (unsigned EI = 0, EE = countof(Extensions); EI != EE; ++EI) {
+    if (Extensions[EI].Extension != Extension)
+      continue;
+
+    unsigned FB = getAvailableFeatures();
+    if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
+      Error(ExtLoc, "architectural extension '" + Extension + "' is not "
+            "allowed for the current base architecture");
+      return false;
+    }
+
+    if (!Extensions[EI].Features)
+      report_fatal_error("unsupported architectural extension: " + Extension);
+
+    if (EnableFeature)
+      FB |= ComputeAvailableFeatures(Extensions[EI].Features);
+    else
+      FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
+
+    setAvailableFeatures(FB);
+    return false;
+  }
+
+  Error(ExtLoc, "unknown architectural extension: " + Extension);
+  Parser.eatToEndOfStatement();
+  return false;
+}
+
 // Define this matcher function after the auto-generated include so we
 // have the match class enum definitions.
 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
diff --git a/test/MC/ARM/directive-arch_extension-crc.s b/test/MC/ARM/directive-arch_extension-crc.s
new file mode 100644
index 00000000000..9e4dedabca4
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-crc.s
@@ -0,0 +1,57 @@
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+
+	.syntax unified
+
+	.arm
+
+	.arch_extension crc
+@ CHECK-V7: error: architectural extension 'crc' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension crc
+@ CHECK-V7-NEXT:                     ^
+
+	.type crc,%function
+crc:
+	crc32b r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+	crc32h r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+	crc32w r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+
+	crc32cb r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+	crc32ch r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+	crc32cw r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+
+	.arch_extension nocrc
+@ CHECK-V7: error: architectural extension 'crc' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension nocrc
+@ CHECK-V7-NEXT:                     ^
+
+	.type nocrc,%function
+nocrc:
+	crc32b r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+@ CHECK-V8: error: instruction requires: crc arm-mode
+	crc32h r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+@ CHECK-V8: error: instruction requires: crc arm-mode
+	crc32w r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+@ CHECK-V8: error: instruction requires: crc arm-mode
+
+	crc32cb r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+@ CHECK-V8: error: instruction requires: crc arm-mode
+	crc32ch r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+@ CHECK-V8: error: instruction requires: crc arm-mode
+	crc32cw r0, r1, r2
+@ CHECK-V7: error: instruction requires: crc armv8
+@ CHECK-V8: error: instruction requires: crc arm-mode
+
diff --git a/test/MC/ARM/directive-arch_extension-crypto.s b/test/MC/ARM/directive-arch_extension-crypto.s
new file mode 100644
index 00000000000..898ba06cf01
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-crypto.s
@@ -0,0 +1,108 @@
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+
+	.syntax unified
+
+	.arch_extension crypto
+@ CHECK-V7: error: architectural extension 'crypto' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension crypto
+@ CHECK-V7-NEXT:                     ^
+
+	.type crypto,%function
+crypto:
+	vmull.p64 q0, d0, d1
+@ CHECK-V7: error: instruction requires: crypto armv8
+
+	aesd.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+	aese.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+	aesimc.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+	aesmc.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+
+	sha1h.32 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha1su1.32 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha256su0.32 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+
+	sha1c.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha1m.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha1p.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha1su0.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha256h.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha256h2.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+	sha256su1.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+
+	.arch_extension nocrypto
+@ CHECK-V7: error: architectural extension 'crypto' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension nocrypto
+@ CHECK-V7-NEXT:                     ^
+
+	.type nocrypto,%function
+nocrypto:
+	vmull.p64 q0, d0, d1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+
+	aesd.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	aese.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	aesimc.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	aesmc.8 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+
+	sha1h.32 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha1su1.32 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha256su0.32 q0, q1
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+
+	sha1c.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha1m.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha1p.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha1su0.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha256h.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha256h2.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+	sha256su1.32 q0, q1, q2
+@ CHECK-V7: error: instruction requires: crypto armv8
+@ CHECK-V8: error: instruction requires: crypto
+
diff --git a/test/MC/ARM/directive-arch_extension-fp.s b/test/MC/ARM/directive-arch_extension-fp.s
new file mode 100644
index 00000000000..0327dd74337
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-fp.s
@@ -0,0 +1,344 @@
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+
+	.syntax unified
+
+	.arch_extension fp
+@ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension fp
+@ CHECK-V7-NEXT:                     ^
+
+	.type fp,%function
+fp:
+	vmrs r0, mvfr2
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vselgt.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vselge.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vseleq.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vselvs.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vmaxnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vminnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vselgt.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vselge.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vseleq.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vselvs.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vmaxnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vminnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vcvtb.f64.f16 d0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtb.f16.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtt.f64.f16 d0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtt.f16.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vcvta.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvta.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvta.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvta.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vrintz.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintz.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintz.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintz.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vrinta.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrinta.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrinta.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrinta.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	.arch_extension nofp
+@ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension nofp
+@ CHECK-V7-NEXT:                     ^
+
+	.type nofp,%function
+nofp:
+	vmrs r0, mvfr2
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+
+	vselgt.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vselge.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vseleq.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vselvs.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vmaxnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vminnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+
+	vselgt.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vselge.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vseleq.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vselvs.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vmaxnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vminnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vcvtb.f64.f16 d0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtb.f16.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtt.f64.f16 d0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtt.f16.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vcvta.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvta.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvta.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvta.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtn.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtn.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtn.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtn.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtp.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtp.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtp.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtp.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtm.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtm.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtm.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtm.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vrintz.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintz.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintz.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintz.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintr.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintr.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintr.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintr.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintx.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintx.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintx.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintx.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vrinta.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrinta.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrinta.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrinta.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintn.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintn.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintn.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintn.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintp.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintp.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintp.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintp.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintm.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintm.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintm.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintm.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
diff --git a/test/MC/ARM/directive-arch_extension-idiv.s b/test/MC/ARM/directive-arch_extension-idiv.s
new file mode 100644
index 00000000000..c63bbfbb4ca
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-idiv.s
@@ -0,0 +1,53 @@
+@ RUN: not llvm-mc -triple armv6-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv6 -check-prefix CHECK-V6
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv7 -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple armv7m-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv7M -check-prefix CHECK-V7M
+@ RUN: not llvm-mc -triple thumbv6-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv6 -check-prefix CHECK-V6
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv7 -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv7M -check-prefix CHECK-V7M
+
+	.syntax unified
+
+	.arch_extension idiv
+@ CHECK-V6: error: architectural extension 'idiv' is not allowed for the current base architecture
+@ CHECK-V6-NEXT: 	.arch_extension idiv
+@ CHECK-V6-NEXT:                     ^
+@ CHECK-V7M: error: architectural extension 'idiv' is not allowed for the current base architecture
+@ CHECK-V7M-NEXT: 	.arch_extension idiv
+@ CHECK-V7M-NEXT:                     ^
+
+	.type idiv,%function
+idiv:
+	udiv r0, r1, r2
+@ CHECK-ARMv6: error: instruction requires: divide in ARM
+@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
+	sdiv r0, r1, r2
+@ CHECK-ARMv6: error: instruction requires: divide in ARM
+@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
+
+	.arch_extension noidiv
+@ CHECK-V6: error: architectural extension 'idiv' is not allowed for the current base architecture
+@ CHECK-V6-NEXT: 	.arch_extension noidiv
+@ CHECK-V6-NEXT:                     ^
+@ CHECK-V7M: error: architectural extension 'idiv' is not allowed for the current base architecture
+@ CHECK-V7M-NEXT: 	.arch_extension noidiv
+@ CHECK-V7M-NEXT:                     ^
+
+	.type noidiv,%function
+noidiv:
+	udiv r0, r1, r2
+@ CHECK-ARMv6: error: instruction requires: divide in ARM
+@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
+@ CHECK-ARMv7: error: instruction requires: divide in ARM arm-mode
+@ CHECK-THUMBv7: error: instruction requires: divide in THUMB
+	sdiv r0, r1, r2
+@ CHECK-ARMv6: error: instruction requires: divide in ARM
+@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode
+@ CHECK-ARMv7: error: instruction requires: divide in ARM arm-mode
+@ CHECK-THUMBv7: error: instruction requires: divide in THUMB
+
diff --git a/test/MC/ARM/directive-arch_extension-mp.s b/test/MC/ARM/directive-arch_extension-mp.s
new file mode 100644
index 00000000000..9046c215315
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-mp.s
@@ -0,0 +1,38 @@
+@ RUN: not llvm-mc -triple armv6-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv6 -check-prefix CHECK-V6
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv7 -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple armv7m-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv7M -check-prefix CHECK-V7M
+@ RUN: not llvm-mc -triple thumbv6-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv6 -check-prefix CHECK-V6
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv7 -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv7M -check-prefix CHECK-V7M
+
+	.syntax unified
+
+	.arch_extension mp
+@ CHECK-V6: error: architectural extension 'mp' is not allowed for the current base architecture
+@ CHECK-V6-NEXT: 	.arch_extension mp
+@ CHECK-V6-NEXT:                     ^
+
+	.type mp,%function
+mp:
+	pldw [r0]
+@ CHECK-V6: error: instruction requires: mp-extensions armv7
+@ CHECK-V7M: error: instruction requires: mp-extensions
+
+	.arch_extension nomp
+@ CHECK-V6: error: architectural extension 'mp' is not allowed for the current base architecture
+@ CHECK-V6-NEXT: 	.arch_extension nomp
+@ CHECK-V6-NEXT:                     ^
+
+	.type nomp,%function
+nomp:
+	pldw [r0]
+@ CHECK-V6: error: instruction requires: mp-extensions armv7
+@ CHECK-V7: error: instruction requires: mp-extensions
+@ CHECK-V7M: error: instruction requires: mp-extensions
+
diff --git a/test/MC/ARM/directive-arch_extension-sec.s b/test/MC/ARM/directive-arch_extension-sec.s
new file mode 100644
index 00000000000..55ead8506ab
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-sec.s
@@ -0,0 +1,31 @@
+@ RUN: not llvm-mc -triple armv6-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv6 -check-prefix CHECK-V6
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ARMv7 -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple thumbv6-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv6 -check-prefix CHECK-V6
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-THUMBv7 -check-prefix CHECK-V7
+
+	.syntax unified
+
+	.arch_extension sec
+@ CHECK-V6: error: architectural extension 'sec' is not allowed for the current base architecture
+@ CHECK-V6-NEXT: 	.arch_extension sec
+@ CHECK-V6-NEXT:                     ^
+
+	.type sec,%function
+sec:
+	smc #0
+@ CHECK-V6: error: instruction requires: TrustZone
+
+	.arch_extension nosec
+@ CHECK-V6: error: architectural extension 'sec' is not allowed for the current base architecture
+@ CHECK-V6-NEXT: 	.arch_extension nosec
+@ CHECK-V6-NEXT:                     ^
+
+	.type nosec,%function
+nosec:
+	smc #0
+@ CHECK-V7: error: instruction requires: TrustZone
+
diff --git a/test/MC/ARM/directive-arch_extension-simd.s b/test/MC/ARM/directive-arch_extension-simd.s
new file mode 100644
index 00000000000..c9dbf21541c
--- /dev/null
+++ b/test/MC/ARM/directive-arch_extension-simd.s
@@ -0,0 +1,275 @@
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V7
+@ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-V8
+
+	.syntax unified
+
+	.arch_extension simd
+@ CHECK-V7: error: architectural extension 'simd' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension simd
+@ CHECK-V7-NEXT:                     ^
+
+	.type simd,%function
+simd:
+	vmaxnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vminnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vmaxnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vminnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vcvta.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvta.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvta.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvta.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtn.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtp.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vcvtm.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vrintz.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintz.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintz.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintz.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintr.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintx.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	vrinta.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrinta.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrinta.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrinta.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintn.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintp.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+	vrintm.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+
+	.arch_extension nosimd
+@ CHECK-V7: error: architectural extension 'simd' is not allowed for the current base architecture
+@ CHECK-V7-NEXT: 	.arch_extension nosimd
+@ CHECK-V7-NEXT:                     ^
+
+	.type nosimd,%function
+nosimd:
+	vmaxnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vminnm.f32 s0, s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+
+	vmaxnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vminnm.f64 d0, d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vcvta.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvta.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvta.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvta.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtn.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtn.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtn.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtn.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtp.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtp.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtp.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtp.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtm.s32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtm.u32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vcvtm.s32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vcvtm.u32.f64 s0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vrintz.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintz.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintz.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintz.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintr.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintr.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintr.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintr.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintx.f32 s0, s1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintx.f64 d0, d1
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintx.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintx.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+
+	vrinta.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrinta.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrinta.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrinta.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintn.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintn.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintn.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintn.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintp.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintp.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintp.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintp.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintm.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintm.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+	vrintm.f32.f32 s0, s0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: FPARMv8
+	vrintm.f64.f64 d0, d0
+@ CHECK-V7: error: instruction requires: FPARMv8
+@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8
+