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Remove filtering concept from X86 disassembler table generation. It's no longer necessary.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201299 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-02-13 07:07:16 +00:00
parent 7a6f5c77c4
commit 1ee7e39dd4
4 changed files with 15 additions and 73 deletions
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2
utils/TableGen/X86DisassemblerShared.h
View File

@ -15,12 +15,10 @@
#define INSTRUCTION_SPECIFIER_FIELDS \
struct OperandSpecifier operands[X86_MAX_OPERANDS]; \
bool filtered; \
InstructionContext insnContext; \
std::string name; \
\
InstructionSpecifier() { \
filtered = false; \
insnContext = IC; \
name = ""; \
memset(operands, 0, sizeof(operands)); \

6
utils/TableGen/X86DisassemblerTables.cpp
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@ -796,9 +796,6 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision,
InstructionSpecifier &previousInfo =
InstructionSpecifiers[decision.instructionIDs[index]];
if(newInfo.filtered)
continue; // filtered instructions get lowest priority
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
// presence of the AdSize prefix. However, the disassembler doesn't
// care about that difference in the instruction definition; it
@ -817,8 +814,7 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision,
if (outranks(previousInfo.insnContext, newInfo.insnContext))
continue;
if (previousInfo.insnContext == newInfo.insnContext &&
!previousInfo.filtered) {
if (previousInfo.insnContext == newInfo.insnContext) {
errs() << "Error: Primary decode conflict: ";
errs() << newInfo.name << " would overwrite " << previousInfo.name;
errs() << "\n";

61
utils/TableGen/X86RecognizableInstr.cpp
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@ -208,6 +208,17 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
}
}
if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
ShouldBeEmitted = false;
return;
}
// Special case since there is no attribute class for 64-bit and VEX
if (Name == "VMASKMOVDQU64") {
ShouldBeEmitted = false;
return;
}
ShouldBeEmitted = true;
}
@ -221,10 +232,10 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
RecognizableInstr recogInstr(tables, insn, uid);
recogInstr.emitInstructionSpecifier();
if (recogInstr.shouldBeEmitted())
if (recogInstr.shouldBeEmitted()) {
recogInstr.emitInstructionSpecifier();
recogInstr.emitDecodePath(tables);
}
}
#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
@ -380,36 +391,6 @@ InstructionContext RecognizableInstr::insnContext() const {
return insnContext;
}
RecognizableInstr::filter_ret RecognizableInstr::filter() const {
///////////////////
// FILTER_STRONG
//
// Filter out intrinsics
assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
return FILTER_STRONG;
// Filter out artificial instructions but leave in the LOCK_PREFIX so it is
// printed as a separate "instruction".
/////////////////
// FILTER_WEAK
//
// Special cases.
if (Name == "VMASKMOVDQU64")
return FILTER_WEAK;
return FILTER_NORMAL;
}
void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
unsigned &physicalOperandIndex,
unsigned &numPhysicalOperands,
@ -445,20 +426,6 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
void RecognizableInstr::emitInstructionSpecifier() {
Spec->name = Name;
if (!ShouldBeEmitted)
return;
switch (filter()) {
case FILTER_WEAK:
Spec->filtered = true;
break;
case FILTER_STRONG:
ShouldBeEmitted = false;
return;
case FILTER_NORMAL:
break;
}
Spec->insnContext = insnContext();
const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;

19
utils/TableGen/X86RecognizableInstr.h
View File

@ -108,25 +108,6 @@ private:
///
/// @return - The context in which the instruction is valid.
InstructionContext insnContext() const;
enum filter_ret {
FILTER_STRONG, // instruction has no place in the instruction tables
FILTER_WEAK, // instruction may conflict, and should be eliminated if
// it does
FILTER_NORMAL // instruction should have high priority and generate an
// error if it conflcits with any other FILTER_NORMAL
// instruction
};
/// filter - Determines whether the instruction should be decodable. Some
/// instructions are pure intrinsics and use unencodable operands; many
/// synthetic instructions are duplicates of other instructions; other
/// instructions only differ in the logical way in which they are used, and
/// have the same decoding. Because these would cause decode conflicts,
/// they must be filtered out.
///
/// @return - The degree of filtering to be applied (see filter_ret).
filter_ret filter() const;
/// hasFROperands - Returns true if any operand is a FR operand.
bool hasFROperands() const;