From 1f347a318c1fa9e542490bdf6f732ef803917fa1 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Thu, 20 Oct 2005 23:58:36 +0000 Subject: [PATCH] Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23852 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaInstrFormats.td | 24 ++++++----- lib/Target/Alpha/AlphaInstrInfo.td | 60 ++++++++++----------------- 2 files changed, 35 insertions(+), 49 deletions(-) diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index fa56bf04da3..efebfd49f47 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -110,7 +110,7 @@ class OForm opcode, bits<7> fun, string asmstr, list pattern> let Inst{4-0} = Rc; } -class OFormT opcode, bits<7> fun, string asmstr, list pattern> +class OForm2 opcode, bits<7> fun, string asmstr, list pattern> : InstAlpha { let Pattern = pattern; @@ -126,13 +126,14 @@ class OFormT opcode, bits<7> fun, string asmstr, list pattern> let Inst{4-0} = Rc; } -class OcmForm opcode, bits<7> fun, dag OL, string asmstr> - : InstAlpha { - bits<5> Ra; - bits<5> Rb; - bits<7> Function = fun; +class OForm4 opcode, bits<7> fun, string asmstr> + : InstAlpha { bits<5> Rc; + bits<5> Rb; + bits<5> Ra; + bits<7> Function = fun; + let isTwoAddress = 1; let Inst{25-21} = Ra; let Inst{20-16} = Rb; let Inst{15-13} = 0; @@ -158,13 +159,14 @@ class OFormL opcode, bits<7> fun, string asmstr, list pattern> let Inst{4-0} = Rc; } -class OcmFormL opcode, bits<7> fun, dag OL, string asmstr> - : InstAlpha { - bits<5> Ra; - bits<8> LIT; - bits<7> Function = fun; +class OForm4L opcode, bits<7> fun, string asmstr> + : InstAlpha { bits<5> Rc; + bits<8> LIT; + bits<5> Ra; + bits<7> Function = fun; + let isTwoAddress = 1; let Inst{25-21} = Ra; let Inst{20-13} = LIT; let Inst{12} = 1; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 943127cb62b..61872a22bcb 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -73,41 +73,25 @@ let isTwoAddress = 1 in { //Operation Form: -let isTwoAddress = 1 in { //conditional moves, int - def CMOVEQ : OcmForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero - def CMOVEQi : OcmFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero - def CMOVGE : OcmForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero - def CMOVGEi : OcmFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero - def CMOVGT : OcmForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero - def CMOVGTi : OcmFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero - def CMOVLBC : OcmForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear - def CMOVLBCi : OcmFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear - def CMOVLBS : OcmForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set - def CMOVLBSi : OcmFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set - def CMOVLE : OcmForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero - def CMOVLEi : OcmFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero - def CMOVLT : OcmForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero - def CMOVLTi : OcmFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero - def CMOVNE : OcmForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), - "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero - def CMOVNEi : OcmFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), - "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero +def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero +def CMOVEQi : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero +def CMOVGE : OForm4< 0x11, 0x46, "cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero +def CMOVGEi : OForm4L< 0x11, 0x46, "cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero +def CMOVGT : OForm4< 0x11, 0x66, "cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero +def CMOVGTi : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero +def CMOVLBC : OForm4< 0x11, 0x16, "cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear +def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear +def CMOVLBS : OForm4< 0x11, 0x14, "cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set +def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set +def CMOVLE : OForm4< 0x11, 0x64, "cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero +def CMOVLEi : OForm4L< 0x11, 0x64, "cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero +def CMOVLT : OForm4< 0x11, 0x44, "cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero +def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero +def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero +def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero +let isTwoAddress = 1 in { //conditional moves, fp def FCMOVEQ : FPFormCM<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero @@ -145,11 +129,11 @@ def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC", [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>; def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC", [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>; -def CTLZ : OFormT<0x1C, 0x32, "CTLZ $RB,$RC", +def CTLZ : OForm2<0x1C, 0x32, "CTLZ $RB,$RC", [(set GPRC:$RC, (ctlz GPRC:$RB))]>; -def CTPOP : OFormT<0x1C, 0x30, "CTPOP $RB,$RC", +def CTPOP : OForm2<0x1C, 0x30, "CTPOP $RB,$RC", [(set GPRC:$RC, (ctpop GPRC:$RB))]>; -def CTTZ : OFormT<0x1C, 0x33, "CTTZ $RB,$RC", +def CTTZ : OForm2<0x1C, 0x33, "CTTZ $RB,$RC", [(set GPRC:$RC, (cttz GPRC:$RB))]>; def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC", [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>; @@ -254,9 +238,9 @@ def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC", [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>; def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC", [(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>; -def SEXTB : OFormT<0x1C, 0x00, "sextb $RB,$RC", +def SEXTB : OForm2<0x1C, 0x00, "sextb $RB,$RC", [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>; -def SEXTW : OFormT<0x1C, 0x01, "sextw $RB,$RC", +def SEXTW : OForm2<0x1C, 0x01, "sextw $RB,$RC", [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))]>; def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC", [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>;