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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
Implement a few new operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43171 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -146,9 +146,11 @@ private:
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void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BSWAP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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@ -177,6 +179,7 @@ private:
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// Operand Expansion.
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// Operand Expansion.
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bool ExpandOperand(SDNode *N, unsigned OperandNo);
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bool ExpandOperand(SDNode *N, unsigned OperandNo);
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SDOperand ExpandOperand_TRUNCATE(SDNode *N);
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SDOperand ExpandOperand_TRUNCATE(SDNode *N);
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SDOperand ExpandOperand_BIT_CONVERT(SDNode *N);
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SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
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SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
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SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
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SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
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SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N);
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SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N);
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@ -639,11 +642,13 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
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case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break;
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case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break;
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case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break;
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case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break;
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case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break;
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case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break;
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case ISD::SIGN_EXTEND_INREG: ExpandResult_SIGN_EXTEND_INREG(N, Lo, Hi); break;
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case ISD::LOAD: ExpandResult_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
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case ISD::LOAD: ExpandResult_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
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case ISD::AND:
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case ISD::AND:
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case ISD::OR:
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case ISD::OR:
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case ISD::XOR: ExpandResult_Logical(N, Lo, Hi); break;
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case ISD::XOR: ExpandResult_Logical(N, Lo, Hi); break;
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case ISD::BSWAP: ExpandResult_BSWAP(N, Lo, Hi); break;
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case ISD::ADD:
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case ISD::ADD:
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case ISD::SUB: ExpandResult_ADDSUB(N, Lo, Hi); break;
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case ISD::SUB: ExpandResult_ADDSUB(N, Lo, Hi); break;
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case ISD::ADDC:
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case ISD::ADDC:
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@ -719,6 +724,22 @@ void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
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ExpandResult_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
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ExpandResult_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
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}
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}
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void DAGTypeLegalizer::
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ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
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GetExpandedOp(N->getOperand(0), Lo, Hi);
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// sext_inreg the low part if needed.
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Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
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N->getOperand(1));
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// The high part gets the sign extension from the lo-part. This handles
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// things like sextinreg V:i64 from i8.
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Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
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DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1,
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TLI.getShiftAmountTy()));
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}
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void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
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void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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SDOperand &Lo, SDOperand &Hi) {
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType VT = N->getValueType(0);
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@ -792,6 +813,14 @@ void DAGTypeLegalizer::ExpandResult_Logical(SDNode *N,
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Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
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Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
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}
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}
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void DAGTypeLegalizer::ExpandResult_BSWAP(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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GetExpandedOp(N->getOperand(0), Hi, Lo); // Note swapped operands.
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Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
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Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
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}
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void DAGTypeLegalizer::ExpandResult_SELECT(SDNode *N,
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void DAGTypeLegalizer::ExpandResult_SELECT(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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SDOperand &Lo, SDOperand &Hi) {
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SDOperand LL, LH, RL, RH;
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SDOperand LL, LH, RL, RH;
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@ -1362,6 +1391,8 @@ bool DAGTypeLegalizer::ExpandOperand(SDNode *N, unsigned OpNo) {
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abort();
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abort();
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case ISD::TRUNCATE: Res = ExpandOperand_TRUNCATE(N); break;
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case ISD::TRUNCATE: Res = ExpandOperand_TRUNCATE(N); break;
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case ISD::BIT_CONVERT: Res = ExpandOperand_BIT_CONVERT(N); break;
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case ISD::SINT_TO_FP:
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case ISD::SINT_TO_FP:
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Res = ExpandOperand_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
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Res = ExpandOperand_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
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break;
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break;
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@ -1401,6 +1432,10 @@ SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) {
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return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
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return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
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}
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}
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SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
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return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
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}
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SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
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SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
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MVT::ValueType DestTy) {
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MVT::ValueType DestTy) {
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// We know the destination is legal, but that the input needs to be expanded.
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// We know the destination is legal, but that the input needs to be expanded.
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