6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-24 08:24:33 +00:00
Code Issues Projects Releases Wiki Activity

DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free

Browse Source 
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2013-07-23 23:55:03 +00:00
parent 8ea83d4999
commit 1f67c63cb2
7 changed files with 61 additions and 190 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -5680,8 +5680,8 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
// fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
// This often reduces constant pool loads.
if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
(N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
(N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
N0.getNode()->hasOneUse() && VT.isInteger() &&
!VT.isVector() && !N0.getValueType().isVector()) {
SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,