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Little patch to turn (shl (add X, 123), 4) -> (add (shl X, 4), 123 << 4)

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This triggers in cases of bitfield additions, opening opportunities for
future improvements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16834 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-10-08 03:46:20 +00:00
parent d74634a885
commit 1f7e160f77
1 changed files with 3 additions and 0 deletions
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3
lib/Transforms/Scalar/InstructionCombining.cpp
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@ -2496,6 +2496,9 @@ Instruction *InstCombiner::visitShiftInst(ShiftInst &I) {
switch (Op0BO->getOpcode()) { switch (Op0BO->getOpcode()) {
default: isValid = false; break; // Do not perform transform! default: isValid = false; break; // Do not perform transform!
case Instruction::Add:
isValid = isLeftShift;
break;
case Instruction::Or: case Instruction::Or:
case Instruction::Xor: case Instruction::Xor:
highBitSet = false; highBitSet = false;