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[ARM64-BE] Predicate VLDR/VSTR for vectors as little-endian only. We must use LD1/ST1 on big-endian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208193 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy
parent
104629cc7c
commit
1f890ce2dc
@ -22,6 +22,8 @@ def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
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AssemblerPredicate<"FeatureCrypto", "crypto">;
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def HasCRC : Predicate<"Subtarget->hasCRC()">,
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AssemblerPredicate<"FeatureCRC", "crc">;
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def IsLE : Predicate<"Subtarget->isLittleEndian()">;
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def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
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//===----------------------------------------------------------------------===//
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// ARM64-specific DAG Nodes.
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@ -1099,20 +1101,26 @@ def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
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(LDRDro ro_indexed64:$addr), dsub)>;
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// Match all load 64 bits width whose type is compatible with FPR64
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def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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let Predicates = [IsLE] in {
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// We must do vector loads with LD1 in big-endian.
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def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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}
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def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
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// Match all load 128 bits width whose type is compatible with FPR128
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def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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let Predicates = [IsLE] in {
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// We must do vector loads with LD1 in big-endian.
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def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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}
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def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
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// Load sign-extended half-word
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@ -1210,20 +1218,26 @@ def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
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(LDRDui am_indexed64:$addr), dsub)>;
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// Match all load 64 bits width whose type is compatible with FPR64
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def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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let Predicates = [IsLE] in {
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// We must use LD1 to perform vector loads in big-endian.
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def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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}
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def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
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// Match all load 128 bits width whose type is compatible with FPR128
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def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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let Predicates = [IsLE] in {
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// We must use LD1 to perform vector loads in big-endian.
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def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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}
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def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
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def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
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@ -1308,7 +1322,7 @@ def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
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def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
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[(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
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def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
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[(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
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[(set (f128 FPR128:$Rt), (load am_unscaled128:$addr))]>;
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def LDURHHi
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: LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
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@ -1318,21 +1332,25 @@ def LDURBBi
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[(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
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// Match all load 64 bits width whose type is compatible with FPR64
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def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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let Predicates = [IsLE] in {
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def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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}
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def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
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// Match all load 128 bits width whose type is compatible with FPR128
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def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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let Predicates = [IsLE] in {
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def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
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}
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// anyext -> zext
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def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
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@ -1628,32 +1646,38 @@ def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
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}
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// Match all store 64 bits width whose type is compatible with FPR64
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def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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}
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def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
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(STRDro FPR64:$Rn, ro_indexed64:$addr)>;
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// Match all store 128 bits width whose type is compatible with FPR128
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def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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}
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def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
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(STRQro FPR128:$Rn, ro_indexed128:$addr)>;
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@ -1676,32 +1700,38 @@ def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
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}
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// Match all store 64 bits width whose type is compatible with FPR64
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def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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}
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def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
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(STRDui FPR64:$Rn, am_indexed64:$addr)>;
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// Match all store 128 bits width whose type is compatible with FPR128
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def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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}
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def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
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(STRQui FPR128:$Rn, am_indexed128:$addr)>;
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@ -1735,41 +1765,47 @@ def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
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def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
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[(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
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def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
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[(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
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[(store (f128 FPR128:$Rt), am_unscaled128:$addr)]>;
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def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
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[(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
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def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
|
||||
[(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
|
||||
|
||||
// Match all store 64 bits width whose type is compatible with FPR64
|
||||
def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
let Predicates = [IsLE] in {
|
||||
// We must use ST1 to store vectors in big-endian.
|
||||
def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
}
|
||||
def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
|
||||
(STURDi FPR64:$Rn, am_unscaled64:$addr)>;
|
||||
|
||||
// Match all store 128 bits width whose type is compatible with FPR128
|
||||
def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
let Predicates = [IsLE] in {
|
||||
// We must use ST1 to store vectors in big-endian.
|
||||
def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
|
||||
(STURQi FPR128:$Rn, am_unscaled128:$addr)>;
|
||||
}
|
||||
|
||||
// unscaled i64 truncating stores
|
||||
def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user