From 1fbf73bae348bcf49f5bcd43a65f11a80d9a513b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 14 May 2015 05:53:56 +0000 Subject: [PATCH] [TableGen] Remove ListInit::size() in favor of getSize() which does the same thing and is already used in most places. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237341 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/TableGen/Record.h | 1 - utils/TableGen/CodeGenRegisters.cpp | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/include/llvm/TableGen/Record.h b/include/llvm/TableGen/Record.h index e1f89d16a2f..b20f29c7eeb 100644 --- a/include/llvm/TableGen/Record.h +++ b/include/llvm/TableGen/Record.h @@ -842,7 +842,6 @@ public: inline const_iterator begin() const { return Values.begin(); } inline const_iterator end () const { return Values.end(); } - inline size_t size () const { return Values.size(); } inline bool empty() const { return Values.empty(); } /// resolveListElementReference - This method is used to implement diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 8d6d3d10d5a..c6940e9fe51 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -676,7 +676,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) // Allocation order 0 is the full set. AltOrders provides others. const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); ListInit *AltOrders = R->getValueAsListInit("AltOrders"); - Orders.resize(1 + AltOrders->size()); + Orders.resize(1 + AltOrders->getSize()); // Default allocation order always contains all registers. for (unsigned i = 0, e = Elements->size(); i != e; ++i) { @@ -689,7 +689,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) // Alternative allocation orders may be subsets. SetTheory::RecSet Order; - for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { + for (unsigned i = 0, e = AltOrders->getSize(); i != e; ++i) { RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); Orders[1 + i].append(Order.begin(), Order.end()); // Verify that all altorder members are regclass members.