From 1fce88313e4d46fdd432b68f7c54fde972c0b526 Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Mon, 1 Apr 2013 15:58:15 +0000
Subject: [PATCH] Add the PPC popcntw instruction

The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCISelLowering.cpp |  2 +-
 lib/Target/PowerPC/PPCInstr64Bit.td    |  7 +++++++
 test/CodeGen/PowerPC/popcnt.ll         | 11 +++++------
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index a0e8e135377..89b42af72e9 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -190,7 +190,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
 
   if (Subtarget->hasPOPCNTD()) {
-    setOperationAction(ISD::CTPOP, MVT::i32  , Promote);
+    setOperationAction(ISD::CTPOP, MVT::i32  , Legal);
     setOperationAction(ISD::CTPOP, MVT::i64  , Legal);
   } else {
     setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 6cc2260de54..61702cf916a 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -468,6 +468,13 @@ def POPCNTD : XForm_11<31, 506, (outs G8RC:$rA), (ins G8RC:$rS),
                       "popcntd $rA, $rS", IntGeneral,
                       [(set i64:$rA, (ctpop i64:$rS))]>;
 
+// popcntw also does a population count on the high 32 bits (storing the
+// results in the high 32-bits of the output). We'll ignore that here (which is
+// safe because we never separately use the high part of the 64-bit registers).
+def POPCNTW : XForm_11<31, 378, (outs GPRC:$rA), (ins GPRC:$rS),
+                      "popcntw $rA, $rS", IntGeneral,
+                      [(set i32:$rA, (ctpop i32:$rS))]>;
+
 def DIVD  : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
                      "divd $rT, $rA, $rB", IntDivD,
                      [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
diff --git a/test/CodeGen/PowerPC/popcnt.ll b/test/CodeGen/PowerPC/popcnt.ll
index 363f7059e44..b304d72aede 100644
--- a/test/CodeGen/PowerPC/popcnt.ll
+++ b/test/CodeGen/PowerPC/popcnt.ll
@@ -4,8 +4,8 @@ define i8 @cnt8(i8 %x) nounwind readnone {
   %cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
   ret i8 %cnt
 ; CHECK: @cnt8
-; CHECK: rldicl
-; CHECK: popcntd
+; CHECK: rlwinm
+; CHECK: popcntw
 ; CHECK: blr
 }
 
@@ -13,8 +13,8 @@ define i16 @cnt16(i16 %x) nounwind readnone {
   %cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
   ret i16 %cnt
 ; CHECK: @cnt16
-; CHECK: rldicl
-; CHECK: popcntd
+; CHECK: rlwinm
+; CHECK: popcntw
 ; CHECK: blr
 }
 
@@ -22,8 +22,7 @@ define i32 @cnt32(i32 %x) nounwind readnone {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
 ; CHECK: @cnt32
-; CHECK: rldicl
-; CHECK: popcntd
+; CHECK: popcntw
 ; CHECK: blr
 }