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Merge an AVX/SSE 256-bit and 128-bit multiclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2757,6 +2757,20 @@ let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
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///
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///
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multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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SDNode OpNode> {
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defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f256mem,
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[(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
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[(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
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(memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
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defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd"), f256mem,
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(bc_v4i64 (v4f64 VR256:$src2))))],
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(memopv4i64 addr:$src2)))], 0>,
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TB, OpSize, VEX_4V, VEX_L;
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// In AVX no need to add a pattern for 128-bit logical rr ps, because they
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// In AVX no need to add a pattern for 128-bit logical rr ps, because they
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// are all promoted to v2i64, and the patterns are covered by the int
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// are all promoted to v2i64, and the patterns are covered by the int
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// version. This is needed in SSE only, because v2i64 isn't supported on
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// version. This is needed in SSE only, because v2i64 isn't supported on
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@ -2773,6 +2787,7 @@ multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))], 0>,
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(memopv2i64 addr:$src2)))], 0>,
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TB, OpSize, VEX_4V;
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TB, OpSize, VEX_4V;
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f128mem,
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!strconcat(OpcodeStr, "ps"), f128mem,
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@ -2789,32 +2804,6 @@ multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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}
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}
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}
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}
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/// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
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///
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multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f256mem,
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[(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
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[(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
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(memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
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defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd"), f256mem,
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(bc_v4i64 (v4f64 VR256:$src2))))],
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(memopv4i64 addr:$src2)))], 0>,
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TB, OpSize, VEX_4V, VEX_L;
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}
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// AVX 256-bit packed logical ops forms
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defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
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defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
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defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
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let isCommutable = 0 in
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defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
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defm AND : sse12_fp_packed_logical<0x54, "and", and>;
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defm AND : sse12_fp_packed_logical<0x54, "and", and>;
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defm OR : sse12_fp_packed_logical<0x56, "or", or>;
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defm OR : sse12_fp_packed_logical<0x56, "or", or>;
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defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
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defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
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