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Prune utf8 chars in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193512 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1106,7 +1106,7 @@ def ShRxRyOffMemX16:
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//
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// Format: SLL rx, ry, sa MIPS16e
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// Purpose: Shift Word Left Logical (Extended)
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// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
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// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
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//
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def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
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@ -1202,7 +1202,7 @@ def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
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// Format: SRA rx, ry, sa MIPS16e
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// Purpose: Shift Word Right Arithmetic (Extended)
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// To execute an arithmetic right-shift of a word by a fixed
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// number of bits—1 to 8 bits.
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// number of bits-1 to 8 bits.
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//
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def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
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@ -1220,7 +1220,7 @@ def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
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// Format: SRL rx, ry, sa MIPS16e
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// Purpose: Shift Word Right Logical (Extended)
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// To execute a logical right-shift of a word by a fixed
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// number of bits—1 to 31 bits.
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// number of bits-1 to 31 bits.
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//
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def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
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@ -1525,8 +1525,8 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
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break;
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}
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// insert_vector_elt (build_vector elt0, …, eltN), NewEltIdx, idx
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// => build_vector elt0, …, NewEltIdx, …, eltN
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// insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
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// => build_vector elt0, ... , NewEltIdx, ... , eltN
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case ISD::INSERT_VECTOR_ELT: {
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SDValue InVec = N->getOperand(0);
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SDValue InVal = N->getOperand(1);
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