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WebAssembly: start instructions
Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,7 +19,7 @@
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "subtarget"
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#define DEBUG_TYPE "wasm-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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@ -40,8 +40,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
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const std::string &CPU,
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const std::string &FS,
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const TargetMachine &TM)
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: WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD(true), CPUString(CPU),
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TargetTriple(TT), FrameLowering(),
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: WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
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CPUString(CPU), TargetTriple(TT), FrameLowering(),
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InstrInfo(initializeSubtargetDependencies(FS)),
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TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
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