mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
* Remove lots of #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@487 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
dcd2fb5f7b
commit
1ff63a1217
@ -9,26 +9,16 @@
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// 7/23/01 - Vikram Adve - Created
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//***************************************************************************
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//************************* System Include Files ***************************/
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#include <hash_set>
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#include <vector>
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#include <algorithm>
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#include <iterator>
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//*************************** User Include Files ***************************/
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Method.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Instruction.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/SchedPriorities.h"
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#include "llvm/Analysis/LiveVar/BBLiveVar.h"
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#include "llvm/CodeGen/TargetMachine.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SchedGraph.h"
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#include "llvm/CodeGen/SchedPriorities.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Instruction.h"
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#include <hash_set>
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#include <algorithm>
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#include <iterator>
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cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
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"enable instruction scheduling debugging information",
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@ -477,7 +467,7 @@ public:
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// Append the instruction to the vector of choices for current cycle.
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// Increment numInClass[c] for the sched class to which the instr belongs.
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choiceVec.push_back(node);
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getMachineInstr()->getOpCode());
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assert(sc < (int) numInClass.size());
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numInClass[sc]++;
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}
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@ -531,11 +521,11 @@ public:
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choicesForSlot[s].erase(node);
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// and decrement the instr count for the sched class to which it belongs
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getMachineInstr()->getOpCode());
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assert(sc < (int) numInClass.size());
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numInClass[sc]--;
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}
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//----------------------------------------------------------------------
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// Create and retrieve delay slot info for delayed instructions
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//----------------------------------------------------------------------
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@ -551,7 +541,7 @@ public:
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if (createIfMissing)
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{
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dinfo = new DelaySlotInfo(bn,
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getInstrInfo().getNumDelaySlots(bn->getOpCode()));
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getInstrInfo().getNumDelaySlots(bn->getMachineInstr()->getOpCode()));
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delaySlotInfoForBranches[bn] = dinfo;
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}
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else
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@ -599,20 +589,20 @@ void
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SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
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cycles_t schedTime)
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{
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if (schedInfo.numBubblesAfter(node->getOpCode()) > 0)
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if (schedInfo.numBubblesAfter(node->getMachineInstr()->getOpCode()) > 0)
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{ // Update next earliest time before which *nothing* can issue.
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nextEarliestIssueTime = max(nextEarliestIssueTime,
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curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
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curTime + 1 + schedInfo.numBubblesAfter(node->getMachineInstr()->getOpCode()));
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}
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const vector<MachineOpCode>*
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conflictVec = schedInfo.getConflictList(node->getOpCode());
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conflictVec = schedInfo.getConflictList(node->getMachineInstr()->getOpCode());
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if (conflictVec != NULL)
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for (unsigned i=0; i < conflictVec->size(); i++)
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{
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MachineOpCode toOp = (*conflictVec)[i];
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cycles_t est = schedTime + schedInfo.getMinIssueGap(node->getOpCode(),
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cycles_t est = schedTime + schedInfo.getMinIssueGap(node->getMachineInstr()->getOpCode(),
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toOp);
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assert(toOp < (int) nextEarliestStartTime.size());
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if (nextEarliestStartTime[toOp] < est)
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@ -834,12 +824,11 @@ ChooseOneGroup(SchedulingManager& S)
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// Print trace of scheduled instructions before newly ready ones
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if (SchedDebugLevel >= Sched_PrintSchedTrace)
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{
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printIndent(2);
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cout << "Cycle " << S.getTime() << " : Scheduled instructions:\n";
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cout << " Cycle " << S.getTime() << " : Scheduled instructions:\n";
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const InstrGroup* igroup = S.isched.getIGroup(S.getTime());
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for (unsigned int s=0; s < S.nslots; s++)
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{
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printIndent(4);
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cout << " ";
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if ((*igroup)[s] != NULL)
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cout << * ((*igroup)[s])->getMachineInstr() << endl;
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else
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@ -923,7 +912,7 @@ FindSlotChoices(SchedulingManager& S,
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if (nextNode == NULL)
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break; // no more instructions for this cycle
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if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0)
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if (S.getInstrInfo().getNumDelaySlots(nextNode->getMachineInstr()->getOpCode()) > 0)
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{
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delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
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if (delaySlotInfo != NULL)
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@ -936,7 +925,7 @@ FindSlotChoices(SchedulingManager& S,
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indexForDelayedInstr = S.getNumChoices();
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}
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}
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else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode()))
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else if (S.schedInfo.breaksIssueGroup(nextNode->getMachineInstr()->getOpCode()))
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{
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if (indexForBreakingNode < S.nslots)
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// have a breaking instruction already so throw this one away
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@ -948,7 +937,7 @@ FindSlotChoices(SchedulingManager& S,
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if (nextNode != NULL)
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S.addChoice(nextNode);
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if (S.schedInfo.isSingleIssue(nextNode->getOpCode()))
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if (S.schedInfo.isSingleIssue(nextNode->getMachineInstr()->getOpCode()))
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{
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assert(S.getNumChoices() == 1 &&
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"Prioritizer returned invalid instr for this cycle!");
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@ -974,7 +963,7 @@ FindSlotChoices(SchedulingManager& S,
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if (S.getNumChoices() == 1)
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{
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MachineOpCode opCode = S.getChoice(0)->getOpCode();
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MachineOpCode opCode = S.getChoice(0)->getMachineInstr()->getOpCode();
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unsigned int s;
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for (s=startSlot; s < S.nslots; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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@ -986,7 +975,7 @@ FindSlotChoices(SchedulingManager& S,
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{
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for (unsigned i=0; i < S.getNumChoices(); i++)
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{
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MachineOpCode opCode = S.getChoice(i)->getOpCode();
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MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
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for (unsigned int s=startSlot; s < S.nslots; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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S.addChoiceToSlot(s, S.getChoice(i));
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@ -1006,7 +995,7 @@ FindSlotChoices(SchedulingManager& S,
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assert(delaySlotInfo != NULL && "No delay slot info for instr?");
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const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
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MachineOpCode delayOpCode = delayedNode->getOpCode();
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MachineOpCode delayOpCode = delayedNode->getMachineInstr()->getOpCode();
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unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
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unsigned delayedNodeSlot = S.nslots;
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@ -1026,7 +1015,7 @@ FindSlotChoices(SchedulingManager& S,
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{
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// Try to assign every other instruction to a lower numbered
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// slot than delayedNodeSlot.
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MachineOpCode opCode = S.getChoice(i)->getOpCode();
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MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
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bool noSlotFound = true;
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unsigned int s;
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for (s=startSlot; s < delayedNodeSlot; s++)
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@ -1080,7 +1069,7 @@ FindSlotChoices(SchedulingManager& S,
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// Find the last possible slot for this instruction.
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for (int s = S.nslots-1; s >= (int) startSlot; s--)
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if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s))
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if (S.schedInfo.instrCanUseSlot(breakingNode->getMachineInstr()->getOpCode(), s))
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{
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breakingSlot = s;
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break;
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@ -1094,7 +1083,7 @@ FindSlotChoices(SchedulingManager& S,
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for (unsigned i=0;
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i < S.getNumChoices() && i < indexForBreakingNode; i++)
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{
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MachineOpCode opCode = S.getChoice(i)->getOpCode();
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MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
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// If a higher priority instruction cannot be assigned to
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// any earlier slots, don't schedule the breaking instruction.
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@ -1134,7 +1123,7 @@ FindSlotChoices(SchedulingManager& S,
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for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++)
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{
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bool foundLowerSlot = false;
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MachineOpCode opCode = S.getChoice(i)->getOpCode();
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MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
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for (unsigned int s=startSlot; s < nslotsToUse; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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S.addChoiceToSlot(s, S.getChoice(i));
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@ -1234,9 +1223,9 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
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return;
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SchedGraphNode* brNode = graph->getGraphNodeForInstr(termMvec[first]);
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assert(! mii.isCall(brNode->getOpCode()) && "Call used as terminator?");
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assert(! mii.isCall(brNode->getMachineInstr()->getOpCode()) && "Call used as terminator?");
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unsigned ndelays = mii.getNumDelaySlots(brNode->getOpCode());
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unsigned ndelays = mii.getNumDelaySlots(brNode->getMachineInstr()->getOpCode());
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if (ndelays == 0)
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return;
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@ -1257,11 +1246,11 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
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for (sg_pred_iterator P = pred_begin(brNode);
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P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
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if (! (*P)->isDummyNode() &&
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! mii.isNop((*P)->getOpCode()) &&
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! mii.isNop((*P)->getMachineInstr()->getOpCode()) &&
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NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
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{
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++numUseful;
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if (mii.maxLatency((*P)->getOpCode()) > 1)
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if (mii.maxLatency((*P)->getMachineInstr()->getOpCode()) > 1)
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mdelayNodeVec.push_back(*P);
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else
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sdelayNodeVec.push_back(*P);
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@ -1275,11 +1264,11 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
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while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
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{
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unsigned latency;
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unsigned minLatency = mii.maxLatency(mdelayNodeVec[0]->getOpCode());
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unsigned minLatency = mii.maxLatency(mdelayNodeVec[0]->getMachineInstr()->getOpCode());
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unsigned minIndex = 0;
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for (unsigned i=1; i < mdelayNodeVec.size(); i++)
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if (minLatency >=
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(latency = mii.maxLatency(mdelayNodeVec[i]->getOpCode())))
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(latency = mii.maxLatency(mdelayNodeVec[i]->getMachineInstr()->getOpCode())))
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{
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minLatency = latency;
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minIndex = i;
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@ -1294,7 +1283,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
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// fill delay slots, otherwise, just discard them.
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for (sg_succ_iterator I=succ_begin(brNode); I != succ_end(brNode); ++I)
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if (! (*I)->isDummyNode()
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&& mii.isNop((*I)->getOpCode()))
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&& mii.isNop((*I)->getMachineInstr()->getOpCode()))
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{
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if (sdelayNodeVec.size() < ndelays)
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sdelayNodeVec.push_back(*I);
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@ -1321,11 +1310,11 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
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assert(! node->isDummyNode());
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// don't put a branch in the delay slot of another branch
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if (S.getInstrInfo().isBranch(node->getOpCode()))
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if (S.getInstrInfo().isBranch(node->getMachineInstr()->getOpCode()))
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return false;
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// don't put a single-issue instruction in the delay slot of a branch
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if (S.schedInfo.isSingleIssue(node->getOpCode()))
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if (S.schedInfo.isSingleIssue(node->getMachineInstr()->getOpCode()))
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return false;
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// don't put a load-use dependence in the delay slot of a branch
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@ -1334,13 +1323,13 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
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for (SchedGraphNode::const_iterator EI = node->beginInEdges();
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EI != node->endInEdges(); ++EI)
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if (! (*EI)->getSrc()->isDummyNode()
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&& mii.isLoad((*EI)->getSrc()->getOpCode())
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&& mii.isLoad((*EI)->getSrc()->getMachineInstr()->getOpCode())
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&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
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return false;
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// for now, don't put an instruction that does not have operand
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// interlocks in the delay slot of a branch
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if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
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if (! S.getInstrInfo().hasOperandInterlock(node->getMachineInstr()->getOpCode()))
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return false;
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// Finally, if the instruction preceeds the branch, we make sure the
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@ -1423,10 +1412,10 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
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{
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const SchedGraphNode* dnode = delayNodeVec[i];
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if ( ! S.isScheduled(dnode)
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&& S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
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&& instrIsFeasible(S, dnode->getOpCode()))
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&& S.schedInfo.instrCanUseSlot(dnode->getMachineInstr()->getOpCode(), nextSlot)
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&& instrIsFeasible(S, dnode->getMachineInstr()->getOpCode()))
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{
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assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpCode())
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assert(S.getInstrInfo().hasOperandInterlock(dnode->getMachineInstr()->getOpCode())
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&& "Instructions without interlocks not yet supported "
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"when filling branch delay slots");
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S.scheduleInstr(dnode, nextSlot, nextTime);
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@ -9,26 +9,16 @@
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// 7/23/01 - Vikram Adve - Created
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//***************************************************************************
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//************************* System Include Files ***************************/
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#include <hash_set>
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#include <vector>
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#include <algorithm>
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#include <iterator>
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//*************************** User Include Files ***************************/
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Method.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Instruction.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/SchedPriorities.h"
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#include "llvm/Analysis/LiveVar/BBLiveVar.h"
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#include "llvm/CodeGen/TargetMachine.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SchedGraph.h"
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#include "llvm/CodeGen/SchedPriorities.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Instruction.h"
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#include <hash_set>
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#include <algorithm>
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#include <iterator>
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cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
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"enable instruction scheduling debugging information",
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@ -477,7 +467,7 @@ public:
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// Append the instruction to the vector of choices for current cycle.
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// Increment numInClass[c] for the sched class to which the instr belongs.
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choiceVec.push_back(node);
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getMachineInstr()->getOpCode());
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assert(sc < (int) numInClass.size());
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numInClass[sc]++;
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}
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@ -531,11 +521,11 @@ public:
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choicesForSlot[s].erase(node);
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// and decrement the instr count for the sched class to which it belongs
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
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const InstrSchedClass& sc = schedInfo.getSchedClass(node->getMachineInstr()->getOpCode());
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assert(sc < (int) numInClass.size());
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numInClass[sc]--;
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}
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//----------------------------------------------------------------------
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// Create and retrieve delay slot info for delayed instructions
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//----------------------------------------------------------------------
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@ -551,7 +541,7 @@ public:
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if (createIfMissing)
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{
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dinfo = new DelaySlotInfo(bn,
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getInstrInfo().getNumDelaySlots(bn->getOpCode()));
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getInstrInfo().getNumDelaySlots(bn->getMachineInstr()->getOpCode()));
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delaySlotInfoForBranches[bn] = dinfo;
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}
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else
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@ -599,20 +589,20 @@ void
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SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
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cycles_t schedTime)
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{
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if (schedInfo.numBubblesAfter(node->getOpCode()) > 0)
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if (schedInfo.numBubblesAfter(node->getMachineInstr()->getOpCode()) > 0)
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{ // Update next earliest time before which *nothing* can issue.
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nextEarliestIssueTime = max(nextEarliestIssueTime,
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curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
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curTime + 1 + schedInfo.numBubblesAfter(node->getMachineInstr()->getOpCode()));
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}
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const vector<MachineOpCode>*
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conflictVec = schedInfo.getConflictList(node->getOpCode());
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conflictVec = schedInfo.getConflictList(node->getMachineInstr()->getOpCode());
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if (conflictVec != NULL)
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for (unsigned i=0; i < conflictVec->size(); i++)
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{
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MachineOpCode toOp = (*conflictVec)[i];
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cycles_t est = schedTime + schedInfo.getMinIssueGap(node->getOpCode(),
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cycles_t est = schedTime + schedInfo.getMinIssueGap(node->getMachineInstr()->getOpCode(),
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toOp);
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assert(toOp < (int) nextEarliestStartTime.size());
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if (nextEarliestStartTime[toOp] < est)
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@ -834,12 +824,11 @@ ChooseOneGroup(SchedulingManager& S)
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// Print trace of scheduled instructions before newly ready ones
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if (SchedDebugLevel >= Sched_PrintSchedTrace)
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{
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printIndent(2);
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cout << "Cycle " << S.getTime() << " : Scheduled instructions:\n";
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cout << " Cycle " << S.getTime() << " : Scheduled instructions:\n";
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const InstrGroup* igroup = S.isched.getIGroup(S.getTime());
|
||||
for (unsigned int s=0; s < S.nslots; s++)
|
||||
{
|
||||
printIndent(4);
|
||||
cout << " ";
|
||||
if ((*igroup)[s] != NULL)
|
||||
cout << * ((*igroup)[s])->getMachineInstr() << endl;
|
||||
else
|
||||
@ -923,7 +912,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
if (nextNode == NULL)
|
||||
break; // no more instructions for this cycle
|
||||
|
||||
if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0)
|
||||
if (S.getInstrInfo().getNumDelaySlots(nextNode->getMachineInstr()->getOpCode()) > 0)
|
||||
{
|
||||
delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
|
||||
if (delaySlotInfo != NULL)
|
||||
@ -936,7 +925,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
indexForDelayedInstr = S.getNumChoices();
|
||||
}
|
||||
}
|
||||
else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode()))
|
||||
else if (S.schedInfo.breaksIssueGroup(nextNode->getMachineInstr()->getOpCode()))
|
||||
{
|
||||
if (indexForBreakingNode < S.nslots)
|
||||
// have a breaking instruction already so throw this one away
|
||||
@ -948,7 +937,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
if (nextNode != NULL)
|
||||
S.addChoice(nextNode);
|
||||
|
||||
if (S.schedInfo.isSingleIssue(nextNode->getOpCode()))
|
||||
if (S.schedInfo.isSingleIssue(nextNode->getMachineInstr()->getOpCode()))
|
||||
{
|
||||
assert(S.getNumChoices() == 1 &&
|
||||
"Prioritizer returned invalid instr for this cycle!");
|
||||
@ -974,7 +963,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
|
||||
if (S.getNumChoices() == 1)
|
||||
{
|
||||
MachineOpCode opCode = S.getChoice(0)->getOpCode();
|
||||
MachineOpCode opCode = S.getChoice(0)->getMachineInstr()->getOpCode();
|
||||
unsigned int s;
|
||||
for (s=startSlot; s < S.nslots; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
@ -986,7 +975,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
{
|
||||
for (unsigned i=0; i < S.getNumChoices(); i++)
|
||||
{
|
||||
MachineOpCode opCode = S.getChoice(i)->getOpCode();
|
||||
MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
|
||||
for (unsigned int s=startSlot; s < S.nslots; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
S.addChoiceToSlot(s, S.getChoice(i));
|
||||
@ -1006,7 +995,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
assert(delaySlotInfo != NULL && "No delay slot info for instr?");
|
||||
|
||||
const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
|
||||
MachineOpCode delayOpCode = delayedNode->getOpCode();
|
||||
MachineOpCode delayOpCode = delayedNode->getMachineInstr()->getOpCode();
|
||||
unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
|
||||
|
||||
unsigned delayedNodeSlot = S.nslots;
|
||||
@ -1026,7 +1015,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
{
|
||||
// Try to assign every other instruction to a lower numbered
|
||||
// slot than delayedNodeSlot.
|
||||
MachineOpCode opCode = S.getChoice(i)->getOpCode();
|
||||
MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
|
||||
bool noSlotFound = true;
|
||||
unsigned int s;
|
||||
for (s=startSlot; s < delayedNodeSlot; s++)
|
||||
@ -1080,7 +1069,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
|
||||
// Find the last possible slot for this instruction.
|
||||
for (int s = S.nslots-1; s >= (int) startSlot; s--)
|
||||
if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s))
|
||||
if (S.schedInfo.instrCanUseSlot(breakingNode->getMachineInstr()->getOpCode(), s))
|
||||
{
|
||||
breakingSlot = s;
|
||||
break;
|
||||
@ -1094,7 +1083,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
for (unsigned i=0;
|
||||
i < S.getNumChoices() && i < indexForBreakingNode; i++)
|
||||
{
|
||||
MachineOpCode opCode = S.getChoice(i)->getOpCode();
|
||||
MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
|
||||
|
||||
// If a higher priority instruction cannot be assigned to
|
||||
// any earlier slots, don't schedule the breaking instruction.
|
||||
@ -1134,7 +1123,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++)
|
||||
{
|
||||
bool foundLowerSlot = false;
|
||||
MachineOpCode opCode = S.getChoice(i)->getOpCode();
|
||||
MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
|
||||
for (unsigned int s=startSlot; s < nslotsToUse; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
S.addChoiceToSlot(s, S.getChoice(i));
|
||||
@ -1234,9 +1223,9 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
|
||||
return;
|
||||
|
||||
SchedGraphNode* brNode = graph->getGraphNodeForInstr(termMvec[first]);
|
||||
assert(! mii.isCall(brNode->getOpCode()) && "Call used as terminator?");
|
||||
assert(! mii.isCall(brNode->getMachineInstr()->getOpCode()) && "Call used as terminator?");
|
||||
|
||||
unsigned ndelays = mii.getNumDelaySlots(brNode->getOpCode());
|
||||
unsigned ndelays = mii.getNumDelaySlots(brNode->getMachineInstr()->getOpCode());
|
||||
if (ndelays == 0)
|
||||
return;
|
||||
|
||||
@ -1257,11 +1246,11 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
|
||||
for (sg_pred_iterator P = pred_begin(brNode);
|
||||
P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
|
||||
if (! (*P)->isDummyNode() &&
|
||||
! mii.isNop((*P)->getOpCode()) &&
|
||||
! mii.isNop((*P)->getMachineInstr()->getOpCode()) &&
|
||||
NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
|
||||
{
|
||||
++numUseful;
|
||||
if (mii.maxLatency((*P)->getOpCode()) > 1)
|
||||
if (mii.maxLatency((*P)->getMachineInstr()->getOpCode()) > 1)
|
||||
mdelayNodeVec.push_back(*P);
|
||||
else
|
||||
sdelayNodeVec.push_back(*P);
|
||||
@ -1275,11 +1264,11 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
|
||||
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
|
||||
{
|
||||
unsigned latency;
|
||||
unsigned minLatency = mii.maxLatency(mdelayNodeVec[0]->getOpCode());
|
||||
unsigned minLatency = mii.maxLatency(mdelayNodeVec[0]->getMachineInstr()->getOpCode());
|
||||
unsigned minIndex = 0;
|
||||
for (unsigned i=1; i < mdelayNodeVec.size(); i++)
|
||||
if (minLatency >=
|
||||
(latency = mii.maxLatency(mdelayNodeVec[i]->getOpCode())))
|
||||
(latency = mii.maxLatency(mdelayNodeVec[i]->getMachineInstr()->getOpCode())))
|
||||
{
|
||||
minLatency = latency;
|
||||
minIndex = i;
|
||||
@ -1294,7 +1283,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
|
||||
// fill delay slots, otherwise, just discard them.
|
||||
for (sg_succ_iterator I=succ_begin(brNode); I != succ_end(brNode); ++I)
|
||||
if (! (*I)->isDummyNode()
|
||||
&& mii.isNop((*I)->getOpCode()))
|
||||
&& mii.isNop((*I)->getMachineInstr()->getOpCode()))
|
||||
{
|
||||
if (sdelayNodeVec.size() < ndelays)
|
||||
sdelayNodeVec.push_back(*I);
|
||||
@ -1321,11 +1310,11 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
|
||||
assert(! node->isDummyNode());
|
||||
|
||||
// don't put a branch in the delay slot of another branch
|
||||
if (S.getInstrInfo().isBranch(node->getOpCode()))
|
||||
if (S.getInstrInfo().isBranch(node->getMachineInstr()->getOpCode()))
|
||||
return false;
|
||||
|
||||
// don't put a single-issue instruction in the delay slot of a branch
|
||||
if (S.schedInfo.isSingleIssue(node->getOpCode()))
|
||||
if (S.schedInfo.isSingleIssue(node->getMachineInstr()->getOpCode()))
|
||||
return false;
|
||||
|
||||
// don't put a load-use dependence in the delay slot of a branch
|
||||
@ -1334,13 +1323,13 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
|
||||
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
|
||||
EI != node->endInEdges(); ++EI)
|
||||
if (! (*EI)->getSrc()->isDummyNode()
|
||||
&& mii.isLoad((*EI)->getSrc()->getOpCode())
|
||||
&& mii.isLoad((*EI)->getSrc()->getMachineInstr()->getOpCode())
|
||||
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
|
||||
return false;
|
||||
|
||||
// for now, don't put an instruction that does not have operand
|
||||
// interlocks in the delay slot of a branch
|
||||
if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
|
||||
if (! S.getInstrInfo().hasOperandInterlock(node->getMachineInstr()->getOpCode()))
|
||||
return false;
|
||||
|
||||
// Finally, if the instruction preceeds the branch, we make sure the
|
||||
@ -1423,10 +1412,10 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
{
|
||||
const SchedGraphNode* dnode = delayNodeVec[i];
|
||||
if ( ! S.isScheduled(dnode)
|
||||
&& S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
|
||||
&& instrIsFeasible(S, dnode->getOpCode()))
|
||||
&& S.schedInfo.instrCanUseSlot(dnode->getMachineInstr()->getOpCode(), nextSlot)
|
||||
&& instrIsFeasible(S, dnode->getMachineInstr()->getOpCode()))
|
||||
{
|
||||
assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpCode())
|
||||
assert(S.getInstrInfo().hasOperandInterlock(dnode->getMachineInstr()->getOpCode())
|
||||
&& "Instructions without interlocks not yet supported "
|
||||
"when filling branch delay slots");
|
||||
S.scheduleInstr(dnode, nextSlot, nextTime);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user