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https://github.com/c64scene-ar/llvm-6502.git
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Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
parent
dd78daa199
commit
1ffe48a84b
@ -67,12 +67,26 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
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}
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RInstruction(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -87,6 +101,57 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
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fieldFromInstruction(Insn, 5, 1) * 5 - 27;
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if (Combined >= 9)
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return MCDisassembler::Fail;
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unsigned Op1High = Combined % 3;
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unsigned Op2High = Combined / 3;
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Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
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Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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return S;
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}
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static DecodeStatus
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DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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return S;
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}
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static DecodeStatus
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Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -73,8 +73,23 @@ class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _F2R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc{5-1};
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let Inst{4} = opc{0};
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let DecoderMethod = "Decode2RInstruction";
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}
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// 2R with first operand as both a source and a destination.
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class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "Decode2RSrcDstInstruction";
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}
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// Same as 2R with last two operands swapped
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class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: _F2R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeR2RInstruction";
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}
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class _FRUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -344,10 +344,9 @@ multiclass FU10_LU10_np<string OpcStr> {
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// Two operand short
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class F2R_np<string OpcStr> : _F2R<
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(outs GRRegs:$dst), (ins GRRegs:$b),
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!strconcat(OpcStr, " $dst, $b"),
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[]>;
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class F2R_np<bits<6> opc, string OpcStr> :
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_F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
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!strconcat(OpcStr, " $dst, $b"), []>;
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// Two operand long
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@ -753,13 +752,11 @@ def BL_lu10 : _FLU10<
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// Two operand short
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// TODO eet, eef, tsetmr
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def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
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"not $dst, $b",
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[(set GRRegs:$dst, (not GRRegs:$b))]>;
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def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
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"not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
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def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
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"neg $dst, $b",
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[(set GRRegs:$dst, (ineg GRRegs:$b))]>;
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def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
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"neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
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let Constraints = "$src1 = $dst" in {
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def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
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@ -777,14 +774,15 @@ def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
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[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
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immBitp:$src2))]>;
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def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
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def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src2, GRRegs:$src1),
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"zext $dst, $src2",
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[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
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GRRegs:$src2))]>;
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def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
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"andnot $dst, $src2",
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[(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
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def ANDNOT_2r :
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_F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
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"andnot $dst, $src2",
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[(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
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}
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let isReMaterializable = 1, neverHasSideEffects = 1 in
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@ -792,99 +790,103 @@ def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
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"mkmsk $dst, $size",
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[]>;
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def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
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"mkmsk $dst, $size",
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[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
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def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
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"mkmsk $dst, $size",
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[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
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def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
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"getr $dst, $type",
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[(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
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def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
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"getts $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
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def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
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"getts $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
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def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
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"setpt res[$r], $val",
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[(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
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def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
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"setpt res[$r], $val",
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[(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
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def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
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"outct res[$r], $val",
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[(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
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def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
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"outct res[$r], $val",
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[(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
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def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
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"outct res[$r], $val",
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[(int_xcore_outct GRRegs:$r, immUs:$val)]>;
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def OUTCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
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"outct res[$r], $val",
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[(int_xcore_outct GRRegs:$r, immUs:$val)]>;
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def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
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"outt res[$r], $val",
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[(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
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def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
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"outt res[$r], $val",
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[(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
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def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
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"out res[$r], $val",
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[(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
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def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
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"out res[$r], $val",
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[(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
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let Constraints = "$src = $dst" in
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def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
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"outshr res[$r], $src",
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[(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r,
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GRRegs:$src))]>;
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def OUTSHR_2r :
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_F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
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"outshr res[$r], $src",
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[(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
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def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
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"inct $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
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def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
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"inct $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
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def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
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"int $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
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def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
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"int $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
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def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
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def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
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"in $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
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let Constraints = "$src = $dst" in
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def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
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"inshr $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r,
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GRRegs:$src))]>;
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def INSHR_2r :
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_F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
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"inshr $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
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def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
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"chkct res[$r], $val",
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[(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
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def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
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"chkct res[$r], $val",
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[(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
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def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
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def CHKCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
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"chkct res[$r], $val",
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[(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
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def TESTCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
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"testct $dst, res[$src]",
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[(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
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def TESTWCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
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"testwct $dst, res[$src]",
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[(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
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def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
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"setd res[$r], $val",
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[(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
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def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
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"setd res[$r], $val",
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[(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
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def GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
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def SETPSC_l2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
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"setpsc res[$src1], $src2",
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[(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
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def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
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"getst $dst, res[$r]",
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[(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
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def INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
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def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
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"init t[$t]:sp, $src",
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[(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
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def INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
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def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
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"init t[$t]:pc, $src",
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[(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
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def INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
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def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
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"init t[$t]:cp, $src",
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[(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
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def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
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def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
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"init t[$t]:dp, $src",
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[(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
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@ -930,10 +932,6 @@ def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
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"setrdy res[$src1], $src2",
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[(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
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def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
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"setpsc res[$src1], $src2",
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[(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
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def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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"peek $dst, res[$src]",
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[(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
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@ -58,3 +58,77 @@
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# CHECK: eeu res[r11]
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0xfb 0x07
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# 2r instructions
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# CHECK: not r1, r8
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0x24 0x8f
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# CHECK: neg r7, r6
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0xce 0x97
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# CHECK: andnot r10, r11
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0xab 0x2f
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# CHECK: mkmsk r11, r0
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0x4c 0xa7
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# CHECK: getts r8, res[r1]
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0x41 0x3f
|
||||
|
||||
# CHECK: setpt res[r2], r3
|
||||
0xde 0x3e
|
||||
|
||||
# CHECK: outct res[r1], r2
|
||||
0xc6 0x4e
|
||||
|
||||
# CHECK: outt res[r5], r4
|
||||
0xd1 0x0f
|
||||
|
||||
# CHECK: out res[r9], r10
|
||||
0xa9 0xaf
|
||||
|
||||
# CHECK: outshr res[r0], r2
|
||||
0xd8 0xae
|
||||
|
||||
# CHECK: inct r7, res[r4]
|
||||
0xdc 0x87
|
||||
|
||||
# CHECK: int r8, res[r3]
|
||||
0x53 0x8f
|
||||
|
||||
# CHECK: in r10, res[r0]
|
||||
0x48 0xb7
|
||||
|
||||
# CHECK: inshr r4, res[r2]
|
||||
0x12 0xb7
|
||||
|
||||
# CHECK: chkct res[r6], r0
|
||||
0x08 0xcf
|
||||
|
||||
# CHECK: testct r8, res[r3]
|
||||
0x53 0xbf
|
||||
|
||||
# CHECK: testwct r2, res[r9]
|
||||
0x39 0xc7
|
||||
|
||||
# CHECK: setd res[r3], r4
|
||||
0x13 0x17
|
||||
|
||||
# CHECK: getst r7, res[r1]
|
||||
0x1d 0x07
|
||||
|
||||
# CHECK: init t[r1]:sp, r2
|
||||
0xc9 0x16
|
||||
|
||||
# CHECK: init t[r10]:pc, r1
|
||||
0x26 0x07
|
||||
|
||||
# CHECK: init t[r2]:cp, r10
|
||||
0x4a 0x1f
|
||||
|
||||
# CHECK: init t[r2]:dp, r3
|
||||
0xce 0x0e
|
||||
|
||||
# CHECK: setpsc res[r8], r2
|
||||
0x28 0xc7
|
||||
|
||||
Loading…
Reference in New Issue
Block a user