mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Eliminate most uses of the machine instruction vector for each LLVM instr,
since some m. instr. may be generated by LLVM instrs. in other blocks. Handle non-SSA (anti and output) edges and true edges uniformly by working with machine instructions alone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1269 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
a95c69997f
commit
200a435966
@ -65,6 +65,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(NULL)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -78,11 +79,12 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(DefUseDep),
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depType(ValueDep),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(_val)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -101,6 +103,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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machineRegNum(_regNum)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -118,6 +121,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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resourceId(_resourceId)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -392,41 +396,36 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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const BasicBlock* bb = term->getParent();
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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const BasicBlock* bb = firstBrNode->getBB();
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const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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if ((*II) == (const Instruction*) term) // special case, handled above
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continue;
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if (mvec[i] == termMvec[first]) // reached the first branch
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break;
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assert(! (*II)->isTerminator() && "Two terminators in basic block?");
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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const MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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}
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@ -580,17 +579,30 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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void
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SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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const RefVec& defVec,
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const Value* defValue,
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const TargetMachine& target)
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SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
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const RefVec& defVec,
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const Value* defValue,
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bool refNodeIsDef,
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const TargetMachine& target)
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{
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// Add edges from all def nodes that are before destNode in the BB.
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// BIGTIME FIXME:
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// We could probably add non-SSA edges here too! But I'll do that later.
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// Add true or output dep edges from all def nodes before refNode in BB.
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// Add anti or output dep edges to all def nodes after refNode.
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for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
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if ((*I).first->getOrigIndexInBB() < destNode->getOrigIndexInBB())
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(void) new SchedGraphEdge((*I).first, destNode, defValue);
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{
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if ((*I).first == refNode)
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continue; // Dont add any self-loops
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if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
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// (*).first is before refNode
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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(refNodeIsDef)? SchedGraphEdge::OutputDep
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: SchedGraphEdge::TrueDep);
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else
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// (*).first is after refNode
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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(refNodeIsDef)? SchedGraphEdge::OutputDep
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: SchedGraphEdge::AntiDep);
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}
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}
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@ -607,12 +619,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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//
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for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
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{
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// ignore def operands here
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if (minstr.operandIsDefined(i))
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continue;
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const MachineOperand& mop = minstr.getOperand(i);
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switch(mop.getOperandType())
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{
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case MachineOperand::MO_VirtualRegister:
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@ -622,7 +629,8 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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{
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ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
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if (I != valueToDefVecMap.end())
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addSSAEdge(node, (*I).second, mop.getVRegValue(), target);
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addEdgesForValue(node, (*I).second, mop.getVRegValue(),
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minstr.operandIsDefined(i), target);
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}
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break;
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@ -651,18 +659,21 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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{
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ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
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if (I != valueToDefVecMap.end())
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addSSAEdge(node, (*I).second, minstr.getImplicitRef(i), target);
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addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
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minstr.implicitRefIsDefined(i), target);
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}
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}
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#undef NEED_SEPARATE_NONSSA_EDGES_CODE
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#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
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void
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SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
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const TargetMachine& target)
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{
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if (isa<PHINode>(instr))
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return;
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MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
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const MachineInstrInfo& mii = target.getInstrInfo();
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RefVec refVec;
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@ -699,13 +710,14 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
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{
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bool prevIsDef = prevNode->getMachineInstr()->
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operandIsDefined(refVec[p].second);
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new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
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new SchedGraphEdge(prevNode, node, SchedGraphEdge::ValueDep,
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(prevIsDef)? SchedGraphEdge::OutputDep
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: SchedGraphEdge::AntiDep);
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}
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}
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}
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}
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#endif NEED_SEPARATE_NONSSA_EDGES_CODE
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void
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@ -920,12 +932,14 @@ SchedGraph::buildGraph(const TargetMachine& target)
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
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#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
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// Then add non-SSA edges for all VM instructions in the block.
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// We assume that all machine instructions that define a value are
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// generated from the VM instruction corresponding to that value.
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// TODO: This could probably be done much more efficiently.
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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this->addNonSSAEdgesForValue(*II, target);
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#endif NEED_SEPARATE_NONSSA_EDGES_CODE
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// Then add edges for dependences on machine registers
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this->addMachineRegEdges(regToRefVecMap, target);
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@ -994,8 +1008,8 @@ operator<<(ostream& os, const SchedGraphEdge& edge)
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switch(edge.depType) {
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case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
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case SchedGraphEdge::DefUseDep: os<< "Reg Value " << edge.val; break;
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case SchedGraphEdge::MemoryDep: os<< "Mem Value " << edge.val; break;
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case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
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case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
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case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
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case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
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default: assert(0); break;
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@ -56,7 +56,7 @@ const ResourceId MachineFPRegsRID = -4; // use +ve numbers for actual regs
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class SchedGraphEdge: public NonCopyable {
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public:
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enum SchedGraphEdgeDepType {
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CtrlDep, MemoryDep, DefUseDep, MachineRegister, MachineResource
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CtrlDep, MemoryDep, ValueDep, MachineRegister, MachineResource
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};
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enum DataDepOrderType {
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TrueDep = 0x1, AntiDep=0x2, OutputDep=0x4, NonDataDep=0x8
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@ -82,21 +82,21 @@ public:
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/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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SchedGraphEdgeDepType _depType,
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unsigned int _depOrderType =TrueDep,
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unsigned int _depOrderType,
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int _minDelay = -1);
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// constructor for explicit def-use or memory def-use edge
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// constructor for explicit value dependence (may be true/anti/output)
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/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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unsigned int _depOrderType =TrueDep,
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unsigned int _depOrderType,
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int _minDelay = -1);
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// constructor for machine register dependence
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/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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unsigned int _depOrderType =TrueDep,
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unsigned int _depOrderType,
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int _minDelay = -1);
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// constructor for any other machine resource dependences.
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@ -115,7 +115,7 @@ public:
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SchedGraphEdgeDepType getDepType () const { return depType; }
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const Value* getValue () const {
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assert(depType == DefUseDep || depType == MemoryDep); return val;
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assert(depType == ValueDep); return val;
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}
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int getMachineReg () const {
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assert(depType == MachineRegister); return machineRegNum;
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@ -335,12 +335,10 @@ private:
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void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target);
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void addSSAEdge (SchedGraphNode* node,
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void addEdgesForValue (SchedGraphNode* refNode,
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const RefVec& defVec,
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const Value* defValue,
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const TargetMachine& target);
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void addNonSSAEdgesForValue (const Instruction* instr,
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bool refNodeIsDef,
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const TargetMachine& target);
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void addDummyEdges ();
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@ -65,6 +65,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(NULL)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -78,11 +79,12 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(DefUseDep),
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depType(ValueDep),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(_val)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -101,6 +103,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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machineRegNum(_regNum)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -118,6 +121,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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resourceId(_resourceId)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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@ -392,41 +396,36 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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const BasicBlock* bb = term->getParent();
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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const BasicBlock* bb = firstBrNode->getBB();
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const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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if ((*II) == (const Instruction*) term) // special case, handled above
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continue;
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if (mvec[i] == termMvec[first]) // reached the first branch
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break;
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assert(! (*II)->isTerminator() && "Two terminators in basic block?");
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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const MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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}
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@ -580,17 +579,30 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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void
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SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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const RefVec& defVec,
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const Value* defValue,
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const TargetMachine& target)
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SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
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const RefVec& defVec,
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const Value* defValue,
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bool refNodeIsDef,
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const TargetMachine& target)
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{
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// Add edges from all def nodes that are before destNode in the BB.
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// BIGTIME FIXME:
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// We could probably add non-SSA edges here too! But I'll do that later.
|
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// Add true or output dep edges from all def nodes before refNode in BB.
|
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// Add anti or output dep edges to all def nodes after refNode.
|
||||
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
|
||||
if ((*I).first->getOrigIndexInBB() < destNode->getOrigIndexInBB())
|
||||
(void) new SchedGraphEdge((*I).first, destNode, defValue);
|
||||
{
|
||||
if ((*I).first == refNode)
|
||||
continue; // Dont add any self-loops
|
||||
|
||||
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
|
||||
// (*).first is before refNode
|
||||
(void) new SchedGraphEdge((*I).first, refNode, defValue,
|
||||
(refNodeIsDef)? SchedGraphEdge::OutputDep
|
||||
: SchedGraphEdge::TrueDep);
|
||||
else
|
||||
// (*).first is after refNode
|
||||
(void) new SchedGraphEdge(refNode, (*I).first, defValue,
|
||||
(refNodeIsDef)? SchedGraphEdge::OutputDep
|
||||
: SchedGraphEdge::AntiDep);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -607,12 +619,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
||||
//
|
||||
for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
|
||||
{
|
||||
// ignore def operands here
|
||||
if (minstr.operandIsDefined(i))
|
||||
continue;
|
||||
|
||||
const MachineOperand& mop = minstr.getOperand(i);
|
||||
|
||||
switch(mop.getOperandType())
|
||||
{
|
||||
case MachineOperand::MO_VirtualRegister:
|
||||
@ -622,7 +629,8 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
||||
{
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addSSAEdge(node, (*I).second, mop.getVRegValue(), target);
|
||||
addEdgesForValue(node, (*I).second, mop.getVRegValue(),
|
||||
minstr.operandIsDefined(i), target);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -651,18 +659,21 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
||||
{
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addSSAEdge(node, (*I).second, minstr.getImplicitRef(i), target);
|
||||
addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
|
||||
minstr.implicitRefIsDefined(i), target);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#undef NEED_SEPARATE_NONSSA_EDGES_CODE
|
||||
#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
|
||||
void
|
||||
SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
||||
const TargetMachine& target)
|
||||
{
|
||||
if (isa<PHINode>(instr))
|
||||
return;
|
||||
|
||||
|
||||
MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
||||
const MachineInstrInfo& mii = target.getInstrInfo();
|
||||
RefVec refVec;
|
||||
@ -699,13 +710,14 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
||||
{
|
||||
bool prevIsDef = prevNode->getMachineInstr()->
|
||||
operandIsDefined(refVec[p].second);
|
||||
new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
|
||||
new SchedGraphEdge(prevNode, node, SchedGraphEdge::ValueDep,
|
||||
(prevIsDef)? SchedGraphEdge::OutputDep
|
||||
: SchedGraphEdge::AntiDep);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif NEED_SEPARATE_NONSSA_EDGES_CODE
|
||||
|
||||
|
||||
void
|
||||
@ -920,12 +932,14 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
|
||||
addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
|
||||
|
||||
#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
|
||||
// Then add non-SSA edges for all VM instructions in the block.
|
||||
// We assume that all machine instructions that define a value are
|
||||
// generated from the VM instruction corresponding to that value.
|
||||
// TODO: This could probably be done much more efficiently.
|
||||
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
||||
this->addNonSSAEdgesForValue(*II, target);
|
||||
#endif NEED_SEPARATE_NONSSA_EDGES_CODE
|
||||
|
||||
// Then add edges for dependences on machine registers
|
||||
this->addMachineRegEdges(regToRefVecMap, target);
|
||||
@ -994,8 +1008,8 @@ operator<<(ostream& os, const SchedGraphEdge& edge)
|
||||
|
||||
switch(edge.depType) {
|
||||
case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
|
||||
case SchedGraphEdge::DefUseDep: os<< "Reg Value " << edge.val; break;
|
||||
case SchedGraphEdge::MemoryDep: os<< "Mem Value " << edge.val; break;
|
||||
case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
|
||||
case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
|
||||
case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
|
||||
case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
|
||||
default: assert(0); break;
|
||||
|
||||
@ -56,7 +56,7 @@ const ResourceId MachineFPRegsRID = -4; // use +ve numbers for actual regs
|
||||
class SchedGraphEdge: public NonCopyable {
|
||||
public:
|
||||
enum SchedGraphEdgeDepType {
|
||||
CtrlDep, MemoryDep, DefUseDep, MachineRegister, MachineResource
|
||||
CtrlDep, MemoryDep, ValueDep, MachineRegister, MachineResource
|
||||
};
|
||||
enum DataDepOrderType {
|
||||
TrueDep = 0x1, AntiDep=0x2, OutputDep=0x4, NonDataDep=0x8
|
||||
@ -82,21 +82,21 @@ public:
|
||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||
SchedGraphNode* _sink,
|
||||
SchedGraphEdgeDepType _depType,
|
||||
unsigned int _depOrderType =TrueDep,
|
||||
unsigned int _depOrderType,
|
||||
int _minDelay = -1);
|
||||
|
||||
// constructor for explicit def-use or memory def-use edge
|
||||
// constructor for explicit value dependence (may be true/anti/output)
|
||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||
SchedGraphNode* _sink,
|
||||
const Value* _val,
|
||||
unsigned int _depOrderType =TrueDep,
|
||||
unsigned int _depOrderType,
|
||||
int _minDelay = -1);
|
||||
|
||||
// constructor for machine register dependence
|
||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||
SchedGraphNode* _sink,
|
||||
unsigned int _regNum,
|
||||
unsigned int _depOrderType =TrueDep,
|
||||
unsigned int _depOrderType,
|
||||
int _minDelay = -1);
|
||||
|
||||
// constructor for any other machine resource dependences.
|
||||
@ -115,7 +115,7 @@ public:
|
||||
SchedGraphEdgeDepType getDepType () const { return depType; }
|
||||
|
||||
const Value* getValue () const {
|
||||
assert(depType == DefUseDep || depType == MemoryDep); return val;
|
||||
assert(depType == ValueDep); return val;
|
||||
}
|
||||
int getMachineReg () const {
|
||||
assert(depType == MachineRegister); return machineRegNum;
|
||||
@ -335,12 +335,10 @@ private:
|
||||
void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
|
||||
const TargetMachine& target);
|
||||
|
||||
void addSSAEdge (SchedGraphNode* node,
|
||||
void addEdgesForValue (SchedGraphNode* refNode,
|
||||
const RefVec& defVec,
|
||||
const Value* defValue,
|
||||
const TargetMachine& target);
|
||||
|
||||
void addNonSSAEdgesForValue (const Instruction* instr,
|
||||
bool refNodeIsDef,
|
||||
const TargetMachine& target);
|
||||
|
||||
void addDummyEdges ();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user