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Detabification. Fixed indentation and spacing.

Browse Source 
Changed cout to DOUT, and TODOs to FIXMEs.
Other changes as per coding conventions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjiv Gupta
2008-05-14 11:31:39 +00:00
parent 6422e8aa1c
commit 2010b3eea6
16 changed files with 527 additions and 608 deletions
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2
lib/Target/PIC16/PIC16.td
View File

@@ -32,7 +32,7 @@ def PIC16InstrInfo : InstrInfo {
// Not currently supported, but work as SubtargetFeature placeholder. // Not currently supported, but work as SubtargetFeature placeholder.
def FeaturePIC16Old : SubtargetFeature<"pic16old", "IsPIC16Old", "true", def FeaturePIC16Old : SubtargetFeature<"pic16old", "IsPIC16Old", "true",
"PIC16 Old ISA Support">; "PIC16 Old ISA Support">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PIC16 processors supported. // PIC16 processors supported.

258
lib/Target/PIC16/PIC16AsmPrinter.cpp
View File

@@ -95,11 +95,11 @@ namespace {
public: public:
void SwitchToTextSection(const char *NewSection, void SwitchToTextSection(const char *NewSection,
const GlobalValue *GV = NULL); const GlobalValue *GV = NULL);
void SwitchToDataSection(const char *NewSection, void SwitchToDataSection(const char *NewSection,
const GlobalValue *GV = NULL); const GlobalValue *GV = NULL);
void SwitchToDataOvrSection(const char *NewSection, void SwitchToDataOvrSection(const char *NewSection,
const GlobalValue *GV = NULL); const GlobalValue *GV = NULL);
}; };
} // end of anonymous namespace } // end of anonymous namespace
@@ -117,7 +117,7 @@ FunctionPass *llvm::createPIC16CodePrinterPass(std::ostream &o,
void PIC16AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const void PIC16AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const
{ {
// Currently unimplemented. // FIXME: Currently unimplemented.
} }
@@ -137,77 +137,70 @@ EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
} else if (ACPV->isStub()) { } else if (ACPV->isStub()) {
FnStubs.insert(Name); FnStubs.insert(Name);
O << TAI->getPrivateGlobalPrefix() << Name << "$stub"; O << TAI->getPrivateGlobalPrefix() << Name << "$stub";
} else } else {
O << Name; O << Name;
if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")"; }
if (ACPV->getPCAdjustment() != 0) { if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
<< utostr(ACPV->getLabelId())
<< "+" << (unsigned)ACPV->getPCAdjustment();
if (ACPV->mustAddCurrentAddress()) if (ACPV->getPCAdjustment() != 0) {
O << "-."; O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
<< utostr(ACPV->getLabelId())
<< "+" << (unsigned)ACPV->getPCAdjustment();
O << ")"; if (ACPV->mustAddCurrentAddress())
} O << "-.";
O << "\n";
// If the constant pool value is a extern weak symbol, remember to emit O << ")";
// the weak reference. }
if (GV && GV->hasExternalWeakLinkage()) O << "\n";
ExtWeakSymbols.insert(GV);
// If the constant pool value is a extern weak symbol, remember to emit
// the weak reference.
if (GV && GV->hasExternalWeakLinkage())
ExtWeakSymbols.insert(GV);
} }
/// Emit the directives used by ASM on the start of functions /// emitFunctionStart - Emit the directives used by ASM on the start of
void PIC16AsmPrinter:: emitFunctionStart(MachineFunction &MF) /// functions.
void PIC16AsmPrinter::emitFunctionStart(MachineFunction &MF)
{ {
// Print out the label for the function. // Print out the label for the function.
const Function *F = MF.getFunction(); const Function *F = MF.getFunction();
MachineFrameInfo *FrameInfo = MF.getFrameInfo(); MachineFrameInfo *FrameInfo = MF.getFrameInfo();
if (FrameInfo->hasStackObjects()) { if (FrameInfo->hasStackObjects()) {
int indexBegin = FrameInfo->getObjectIndexBegin(); int indexBegin = FrameInfo->getObjectIndexBegin();
int indexEnd = FrameInfo->getObjectIndexEnd(); int indexEnd = FrameInfo->getObjectIndexEnd();
while (indexBegin<indexEnd) { while (indexBegin < indexEnd) {
if (indexBegin ==0) if (indexBegin == 0)
SwitchToDataOvrSection(F->getParent()->getModuleIdentifier().c_str(), SwitchToDataOvrSection(F->getParent()->getModuleIdentifier().c_str(),
F); F);
O << "\t\t" << CurrentFnName << "_" << indexBegin << " " << "RES" O << "\t\t" << CurrentFnName << "_" << indexBegin << " " << "RES"
<< " " << FrameInfo->getObjectSize(indexBegin) << "\n" ; << " " << FrameInfo->getObjectSize(indexBegin) << "\n" ;
indexBegin++; indexBegin++;
} }
} }
SwitchToTextSection(CurrentFnName.c_str(), F); SwitchToTextSection(CurrentFnName.c_str(), F);
O << "_" << CurrentFnName << ":" ; O << "_" << CurrentFnName << ":" ;
O << "\n"; O << "\n";
} }
/// runOnMachineFunction - This uses the printInstruction() /// runOnMachineFunction - This uses the printInstruction()
/// method to print assembly for each instruction. /// method to print assembly for each instruction.
/// ///
bool PIC16AsmPrinter:: bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction(MachineFunction &MF)
{ {
// DW.SetModuleInfo(&getAnalysis<MachineModuleInfo>());
SetupMachineFunction(MF); SetupMachineFunction(MF);
O << "\n"; O << "\n";
// NOTE: we don't print out constant pools here, they are handled as
// instructions.
O << "\n";
// What's my mangled name? // What's my mangled name?
CurrentFnName = Mang->getValueName(MF.getFunction()); CurrentFnName = Mang->getValueName(MF.getFunction());
// Emit the function start directives // Emit the function start directives
emitFunctionStart(MF); emitFunctionStart(MF);
// Emit pre-function debug information.
// DW.BeginFunction(&MF);
// Print out code for the function. // Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) { I != E; ++I) {
@@ -225,9 +218,6 @@ runOnMachineFunction(MachineFunction &MF)
} }
} }
// Emit post-function debug information.
// DW.EndFunction();
// We didn't modify anything. // We didn't modify anything.
return false; return false;
} }
@@ -238,61 +228,50 @@ printOperand(const MachineInstr *MI, int opNum, const char *Modifier)
const MachineOperand &MO = MI->getOperand(opNum); const MachineOperand &MO = MI->getOperand(opNum);
const TargetRegisterInfo &RI = *TM.getRegisterInfo(); const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) switch (MO.getType()) {
{
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
{
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << RI.get(MO.getReg()).Name; O << RI.get(MO.getReg()).Name;
else else
assert(0 && "not implemented"); assert(0 && "not implemented");
break; break;
}
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
{
if (!Modifier || strcmp(Modifier, "no_hash") != 0) if (!Modifier || strcmp(Modifier, "no_hash") != 0)
O << "#"; O << "#";
O << (int)MO.getImm(); O << (int)MO.getImm();
break; break;
}
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:
{
printBasicBlockLabel(MO.getMBB()); printBasicBlockLabel(MO.getMBB());
return; return;
}
case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_GlobalAddress:
{
O << Mang->getValueName(MO.getGlobal())<<'+'<<MO.getOffset(); O << Mang->getValueName(MO.getGlobal())<<'+'<<MO.getOffset();
break; break;
}
case MachineOperand::MO_ExternalSymbol: case MachineOperand::MO_ExternalSymbol:
{
O << MO.getSymbolName(); O << MO.getSymbolName();
break; break;
}
case MachineOperand::MO_ConstantPoolIndex: case MachineOperand::MO_ConstantPoolIndex:
{
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
<< '_' << MO.getIndex(); << '_' << MO.getIndex();
break; break;
}
case MachineOperand::MO_FrameIndex: case MachineOperand::MO_FrameIndex:
{
O << "_" << CurrentFnName O << "_" << CurrentFnName
<< '+' << MO.getIndex(); << '+' << MO.getIndex();
break; break;
}
case MachineOperand::MO_JumpTableIndex: case MachineOperand::MO_JumpTableIndex:
{
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << MO.getIndex(); << '_' << MO.getIndex();
break; break;
}
default: default:
{
O << "<unknown operand type>"; abort (); O << "<unknown operand type>"; abort ();
break; break;
}
} // end switch. } // end switch.
} }
@@ -300,15 +279,13 @@ static void
printSOImm(std::ostream &O, int64_t V, const TargetAsmInfo *TAI) printSOImm(std::ostream &O, int64_t V, const TargetAsmInfo *TAI)
{ {
assert(V < (1 << 12) && "Not a valid so_imm value!"); assert(V < (1 << 12) && "Not a valid so_imm value!");
unsigned Imm = V;
O << Imm; O << (unsigned) V;
} }
/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// printSOImmOperand - SOImm is 4-bit rotated amount in bits 8-11 with 8-bit
/// immediate in bits 0-7. /// immediate in bits 0-7.
void PIC16AsmPrinter:: void PIC16AsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum)
printSOImmOperand(const MachineInstr *MI, int OpNum)
{ {
const MachineOperand &MO = MI->getOperand(OpNum); const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!"); assert(MO.isImmediate() && "Not a valid so_imm value!");
@@ -316,7 +293,7 @@ printSOImmOperand(const MachineInstr *MI, int OpNum)
} }
void PIC16AsmPrinter:: printAddrModeOperand(const MachineInstr *MI, int Op) void PIC16AsmPrinter::printAddrModeOperand(const MachineInstr *MI, int Op)
{ {
const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO2 = MI->getOperand(Op+1);
@@ -326,15 +303,15 @@ void PIC16AsmPrinter:: printAddrModeOperand(const MachineInstr *MI, int Op)
return; return;
} }
if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right. if (!MO1.isRegister()) {
// FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op); printOperand(MI, Op);
return; return;
} }
// If this is Stack Slot // If this is Stack Slot
if (MO1.isRegister()) { if (MO1.isRegister()) {
if(strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name, "SP")==0) if (strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name, "SP") == 0) {
{
O << CurrentFnName <<"_"<< MO2.getImm(); O << CurrentFnName <<"_"<< MO2.getImm();
return; return;
} }
@@ -350,7 +327,7 @@ void PIC16AsmPrinter:: printAddrModeOperand(const MachineInstr *MI, int Op)
} }
void PIC16AsmPrinter:: printRegisterList(const MachineInstr *MI, int opNum) void PIC16AsmPrinter::printRegisterList(const MachineInstr *MI, int opNum)
{ {
O << "{"; O << "{";
for (unsigned i = opNum, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = opNum, e = MI->getNumOperands(); i != e; ++i) {
@@ -391,16 +368,13 @@ printCPInstOperand(const MachineInstr *MI, int OpNo, const char *Modifier)
} }
bool PIC16AsmPrinter:: doInitialization(Module &M) bool PIC16AsmPrinter::doInitialization(Module &M)
{ {
// Emit initial debug information.
// DW.BeginModule(&M);
bool Result = AsmPrinter::doInitialization(M); bool Result = AsmPrinter::doInitialization(M);
return Result; return Result;
} }
bool PIC16AsmPrinter:: doFinalization(Module &M) bool PIC16AsmPrinter::doFinalization(Module &M)
{ {
const TargetData *TD = TM.getTargetData(); const TargetData *TD = TM.getTargetData();
@@ -415,8 +389,8 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
std::string name = Mang->getValueName(I); std::string name = Mang->getValueName(I);
Constant *C = I->getInitializer(); Constant *C = I->getInitializer();
const Type *Type = C->getType(); const Type *Ty = C->getType();
unsigned Size = TD->getABITypeSize(Type); unsigned Size = TD->getABITypeSize(Ty);
unsigned Align = TD->getPreferredAlignmentLog(I); unsigned Align = TD->getPreferredAlignmentLog(I);
const char *VisibilityDirective = NULL; const char *VisibilityDirective = NULL;
@@ -443,7 +417,7 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
I->hasLinkOnceLinkage())) { I->hasLinkOnceLinkage())) {
if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it. if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
if (!NoZerosInBSS && TAI->getBSSSection()) if (!NoZerosInBSS && TAI->getBSSSection())
SwitchToDataSection(M.getModuleIdentifier().c_str(), I); SwitchToDataSection(M.getModuleIdentifier().c_str(), I);
else else
SwitchToDataSection(TAI->getDataSection(), I); SwitchToDataSection(TAI->getDataSection(), I);
if (TAI->getLCOMMDirective() != NULL) { if (TAI->getLCOMMDirective() != NULL) {
@@ -453,33 +427,29 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
O << TAI->getCOMMDirective() << name << "," << Size; O << TAI->getCOMMDirective() << name << "," << Size;
} else { } else {
if (I->hasInternalLinkage()) if (I->hasInternalLinkage())
O << "\t.local\t" << name << "\n"; O << "\t.local\t" << name << "\n";
O << TAI->getCOMMDirective() <<"\t" << name << " " <<"RES"<< " " O << TAI->getCOMMDirective() <<"\t" << name << " " <<"RES"<< " "
<< Size; << Size;
O << "\n\t\tGLOBAL" <<" "<< name; O << "\n\t\tGLOBAL" <<" "<< name;
if (TAI->getCOMMDirectiveTakesAlignment()) if (TAI->getCOMMDirectiveTakesAlignment())
O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align); O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
} }
continue; continue;
} }
} }
switch (I->getLinkage()) switch (I->getLinkage()) {
{
case GlobalValue::AppendingLinkage: case GlobalValue::AppendingLinkage:
{
// FIXME: appending linkage variables should go into a section of // FIXME: appending linkage variables should go into a section of
// their name or something. For now, just emit them as external. // their name or something. For now, just emit them as external.
// Fall through // FALL THROUGH
}
case GlobalValue::ExternalLinkage: case GlobalValue::ExternalLinkage:
{
O << "\t.globl " << name << "\n"; O << "\t.globl " << name << "\n";
// FALL THROUGH // FALL THROUGH
}
case GlobalValue::InternalLinkage: case GlobalValue::InternalLinkage:
{
if (I->isConstant()) { if (I->isConstant()) {
const ConstantArray *CVA = dyn_cast<ConstantArray>(C); const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
if (TAI->getCStringSection() && CVA && CVA->isCString()) { if (TAI->getCStringSection() && CVA && CVA->isCString()) {
@@ -488,12 +458,10 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
} }
} }
break; break;
}
default: default:
{
assert(0 && "Unknown linkage type!"); assert(0 && "Unknown linkage type!");
break; break;
}
} // end switch. } // end switch.
EmitAlignment(Align, I); EmitAlignment(Align, I);
@@ -517,53 +485,53 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
void PIC16AsmPrinter:: void PIC16AsmPrinter::
SwitchToTextSection(const char *NewSection, const GlobalValue *GV) SwitchToTextSection(const char *NewSection, const GlobalValue *GV)
{ {
O << "\n"; O << "\n";
if (NewSection && *NewSection) { if (NewSection && *NewSection) {
std::string codeSection = "code_"; std::string codeSection = "code_";
codeSection += NewSection; codeSection += NewSection;
codeSection += " "; codeSection += " ";
codeSection += "CODE"; codeSection += "CODE";
AsmPrinter::SwitchToTextSection(codeSection.c_str(),GV); AsmPrinter::SwitchToTextSection(codeSection.c_str(), GV);
} }
else else
AsmPrinter::SwitchToTextSection(NewSection,GV); AsmPrinter::SwitchToTextSection(NewSection, GV);
} }
void PIC16AsmPrinter:: void PIC16AsmPrinter::
SwitchToDataSection(const char *NewSection, const GlobalValue *GV) SwitchToDataSection(const char *NewSection, const GlobalValue *GV)
{ {
//Need to append index for page // Need to append index for page.
O << "\n"; O << "\n";
if (NewSection && *NewSection) { if (NewSection && *NewSection) {
std::string dataSection ="udata_"; std::string dataSection = "udata_";
dataSection+=NewSection; dataSection += NewSection;
if (dataSection.substr(dataSection.length()-2).compare(".o") == 0) { if (dataSection.substr(dataSection.length() - 2).compare(".o") == 0) {
dataSection = dataSection.substr(0,dataSection.length()-2); dataSection = dataSection.substr(0, dataSection.length() - 2);
} }
dataSection += " "; dataSection += " ";
dataSection += "UDATA"; dataSection += "UDATA";
AsmPrinter::SwitchToDataSection(dataSection.c_str(),GV); AsmPrinter::SwitchToDataSection(dataSection.c_str(), GV);
} }
else else
AsmPrinter::SwitchToDataSection(NewSection,GV); AsmPrinter::SwitchToDataSection(NewSection, GV);
} }
void PIC16AsmPrinter:: void PIC16AsmPrinter::
SwitchToDataOvrSection(const char *NewSection, const GlobalValue *GV) SwitchToDataOvrSection(const char *NewSection, const GlobalValue *GV)
{ {
O << "\n"; O << "\n";
if (NewSection && *NewSection) { if (NewSection && *NewSection) {
std::string dataSection = "frame_"; std::string dataSection = "frame_";
dataSection += NewSection; dataSection += NewSection;
if (dataSection.substr(dataSection.length()-2).compare(".o") == 0) { if (dataSection.substr(dataSection.length() - 2).compare(".o") == 0) {
dataSection = dataSection.substr(0,dataSection.length()-2); dataSection = dataSection.substr(0, dataSection.length() - 2);
} }
dataSection += "_"; dataSection += "_";
dataSection += CurrentFnName; dataSection += CurrentFnName;
dataSection += " "; dataSection += " ";
dataSection += "UDATA_OVR"; dataSection += "UDATA_OVR";
AsmPrinter::SwitchToDataSection(dataSection.c_str(),GV); AsmPrinter::SwitchToDataSection(dataSection.c_str(), GV);
} }
else else
AsmPrinter::SwitchToDataSection(NewSection,GV); AsmPrinter::SwitchToDataSection(NewSection, GV);
} }

3
lib/Target/PIC16/PIC16CallingConv.td
View File

@@ -1,4 +1,4 @@
//===- PIC16CallingConv.td - Calling Conventions Sparc -----*- tablegen -*-===// //===- PIC16CallingConv.td - Calling Conventions PIC16 -----*- tablegen -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@@ -14,4 +14,3 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Return Value Calling Conventions // Return Value Calling Conventions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

14
lib/Target/PIC16/PIC16ConstantPoolValue.h
View File

@@ -41,15 +41,15 @@ class PIC16ConstantPoolValue : public MachineConstantPoolValue {
public: public:
PIC16ConstantPoolValue(GlobalValue *gv, unsigned id, PIC16ConstantPoolValue(GlobalValue *gv, unsigned id,
PIC16CP::PIC16CPKind Kind = PIC16CP::CPValue, PIC16CP::PIC16CPKind Kind = PIC16CP::CPValue,
unsigned char PCAdj = 0, const char *Modifier = NULL, unsigned char PCAdj = 0, const char *Modifier = NULL,
bool AddCurrentAddress = false); bool AddCurrentAddress = false);
PIC16ConstantPoolValue(const char *s, unsigned id, PIC16ConstantPoolValue(const char *s, unsigned id,
PIC16CP::PIC16CPKind Kind = PIC16CP::CPValue, PIC16CP::PIC16CPKind Kind = PIC16CP::CPValue,
unsigned char PCAdj = 0, const char *Modifier = NULL, unsigned char PCAdj = 0, const char *Modifier = NULL,
bool AddCurrentAddress = false); bool AddCurrentAddress = false);
PIC16ConstantPoolValue(GlobalValue *GV, PIC16CP::PIC16CPKind Kind, PIC16ConstantPoolValue(GlobalValue *GV, PIC16CP::PIC16CPKind Kind,
const char *Modifier); const char *Modifier);
GlobalValue *getGV() const { return GV; } GlobalValue *getGV() const { return GV; }

60
lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
View File

@@ -56,11 +56,6 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
/// PIC16-specific SelectionDAG. /// PIC16-specific SelectionDAG.
PIC16TargetLowering PIC16Lowering; PIC16TargetLowering PIC16Lowering;
/// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
/// make the right decision when generating code for different targets.
//TODO: add initialization on constructor
//const PIC16Subtarget *Subtarget;
public: public:
PIC16DAGToDAGISel(PIC16TargetMachine &tm) : PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
SelectionDAGISel(PIC16Lowering), SelectionDAGISel(PIC16Lowering),
@@ -75,18 +70,18 @@ public:
private: private:
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "PIC16GenDAGISel.inc" #include "PIC16GenDAGISel.inc"
SDNode *Select(SDOperand N); SDNode *Select(SDOperand N);
// Select addressing mode. currently assume base + offset addr mode. // Select addressing mode. currently assume base + offset addr mode.
bool SelectAM(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset); bool SelectAM(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset);
bool SelectDirectAM(SDOperand Op, SDOperand N, SDOperand &Base, bool SelectDirectAM(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset); SDOperand &Offset);
bool StoreInDirectAM(SDOperand Op, SDOperand N, SDOperand &fsr); bool StoreInDirectAM(SDOperand Op, SDOperand N, SDOperand &fsr);
bool LoadFSR(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset); bool LoadFSR(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset);
bool LoadNothing(SDOperand Op, SDOperand N, SDOperand &Base, bool LoadNothing(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset); SDOperand &Offset);
// getI8Imm - Return a target constant with the specified // getI8Imm - Return a target constant with the specified
// value, of type i8. // value, of type i8.
@@ -95,9 +90,9 @@ private:
} }
#ifndef NDEBUG #ifndef NDEBUG
unsigned Indent; unsigned Indent;
#endif #endif
}; };
} }
@@ -108,17 +103,16 @@ void PIC16DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &SD)
{ {
DEBUG(BB->dump()); DEBUG(BB->dump());
// Codegen the basic block. // Codegen the basic block.
#ifndef NDEBUG
DOUT << "===== Instruction selection begins:\n"; DOUT << "===== Instruction selection begins:\n";
#ifndef NDEBUG
Indent = 0; Indent = 0;
#endif #endif
// Select target instructions for the DAG. // Select target instructions for the DAG.
SD.setRoot(SelectRoot(SD.getRoot())); SD.setRoot(SelectRoot(SD.getRoot()));
#ifndef NDEBUG
DOUT << "===== Instruction selection ends:\n"; DOUT << "===== Instruction selection ends:\n";
#endif
SD.RemoveDeadNodes(); SD.RemoveDeadNodes();
@@ -135,7 +129,7 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
// if Address is FI, get the TargetFrameIndex. // if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
cout << "--------- its frame Index\n"; DOUT << "--------- its frame Index\n";
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
@@ -154,11 +148,11 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
Offset = CurDAG->getTargetConstant((unsigned char)GC->getValue(), MVT::i8); Offset = CurDAG->getTargetConstant((unsigned char)GC->getValue(), MVT::i8);
if ((GA = dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))) { if ((GA = dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))) {
Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16, Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
GC->getValue()); GC->getValue());
return true; return true;
} }
else if (FrameIndexSDNode *FIN else if (FrameIndexSDNode *FIN
= dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
return true; return true;
} }
@@ -168,7 +162,7 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
} }
//FIXME: must also account for preinc/predec/postinc/postdec // FIXME: must also account for preinc/predec/postinc/postdec.
bool PIC16DAGToDAGISel:: bool PIC16DAGToDAGISel::
StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr) StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
{ {
@@ -181,12 +175,12 @@ StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
else if (isa<RegisterSDNode>(N.Val)) { else if (isa<RegisterSDNode>(N.Val)) {
//FIXME an attempt to retrieve the register number //FIXME an attempt to retrieve the register number
//but does not work //but does not work
cout << "this is a register\n"; DOUT << "this is a register\n";
Reg = dyn_cast<RegisterSDNode>(N.Val); Reg = dyn_cast<RegisterSDNode>(N.Val);
fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16); fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);
} }
else { else {
cout << "this is not a register\n"; DOUT << "this is not a register\n";
// FIXME must use whatever load is using // FIXME must use whatever load is using
fsr = CurDAG->getRegister(1,MVT::i16); fsr = CurDAG->getRegister(1,MVT::i16);
} }
@@ -204,7 +198,7 @@ LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
GA = dyn_cast<GlobalAddressSDNode>(N); GA = dyn_cast<GlobalAddressSDNode>(N);
Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8); Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8);
Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16, Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
GA->getOffset()); GA->getOffset());
return true; return true;
} }
else if (N.getOpcode() == PIC16ISD::Package) { else if (N.getOpcode() == PIC16ISD::Package) {
@@ -215,17 +209,17 @@ LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
return false; return false;
} }
//don't thake this seriously, it will change // LoadNothing - Don't thake this seriously, it will change.
bool PIC16DAGToDAGISel:: bool PIC16DAGToDAGISel::
LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
{ {
GlobalAddressSDNode *GA; GlobalAddressSDNode *GA;
if (N.getOpcode() == ISD::GlobalAddress) { if (N.getOpcode() == ISD::GlobalAddress) {
GA = dyn_cast<GlobalAddressSDNode>(N); GA = dyn_cast<GlobalAddressSDNode>(N);
cout << "==========" << GA->getOffset() << "\n"; DOUT << "==========" << GA->getOffset() << "\n";
Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8); Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8);
Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16, Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
GA->getOffset()); GA->getOffset());
return true; return true;
} }
@@ -233,34 +227,34 @@ LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
} }
/// Select instructions not customized! Used for /// Select - Select instructions not customized! Used for
/// expanded, promoted and normal instructions /// expanded, promoted and normal instructions.
SDNode* PIC16DAGToDAGISel::Select(SDOperand N) SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
{ {
SDNode *Node = N.Val; SDNode *Node = N.Val;
unsigned Opcode = Node->getOpcode(); unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected // Dump information about the Node being selected
#ifndef NDEBUG #ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: "; DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG)); DEBUG(Node->dump(CurDAG));
DOUT << "\n"; DOUT << "\n";
Indent += 2; Indent += 2;
#endif #endif
// If we have a custom node, we already have selected! // If we have a custom node, we already have selected!
if (Opcode >= ISD::BUILTIN_OP_END && Opcode < PIC16ISD::FIRST_NUMBER) { if (Opcode >= ISD::BUILTIN_OP_END && Opcode < PIC16ISD::FIRST_NUMBER) {
#ifndef NDEBUG #ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "== "; DOUT << std::string(Indent-2, ' ') << "== ";
DEBUG(Node->dump(CurDAG)); DEBUG(Node->dump(CurDAG));
DOUT << "\n"; DOUT << "\n";
Indent -= 2; Indent -= 2;
#endif #endif
return NULL; return NULL;
} }
/// ///
// Instruction Selection not handled by custom or by the // FIXME: Instruction Selection not handled by custom or by the
// auto-generated tablegen selection should be handled here. // auto-generated tablegen selection should be handled here.
/// ///
switch(Opcode) { switch(Opcode) {
@@ -270,7 +264,7 @@ SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
// Select the default instruction. // Select the default instruction.
SDNode *ResNode = SelectCode(N); SDNode *ResNode = SelectCode(N);
#ifndef NDEBUG #ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> "; DOUT << std::string(Indent-2, ' ') << "=> ";
if (ResNode == NULL || ResNode == N.Val) if (ResNode == NULL || ResNode == N.Val)
DEBUG(N.Val->dump(CurDAG)); DEBUG(N.Val->dump(CurDAG));
@@ -278,7 +272,7 @@ SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
DEBUG(ResNode->dump(CurDAG)); DEBUG(ResNode->dump(CurDAG));
DOUT << "\n"; DOUT << "\n";
Indent -= 2; Indent -= 2;
#endif #endif
return ResNode; return ResNode;
} }

621
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@@ -35,8 +35,7 @@ using namespace llvm;
const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
{ {
switch (Opcode) switch (Opcode) {
{
case PIC16ISD::Hi : return "PIC16ISD::Hi"; case PIC16ISD::Hi : return "PIC16ISD::Hi";
case PIC16ISD::Lo : return "PIC16ISD::Lo"; case PIC16ISD::Lo : return "PIC16ISD::Lo";
case PIC16ISD::Package : return "PIC16ISD::Package"; case PIC16ISD::Package : return "PIC16ISD::Package";
@@ -44,7 +43,7 @@ const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
case PIC16ISD::SetBank : return "PIC16ISD::SetBank"; case PIC16ISD::SetBank : return "PIC16ISD::SetBank";
case PIC16ISD::SetPage : return "PIC16ISD::SetPage"; case PIC16ISD::SetPage : return "PIC16ISD::SetPage";
case PIC16ISD::Branch : return "PIC16ISD::Branch"; case PIC16ISD::Branch : return "PIC16ISD::Branch";
case PIC16ISD::Cmp : return "PIC16ISD::Cmp"; case PIC16ISD::Cmp : return "PIC16ISD::Cmp";
case PIC16ISD::BTFSS : return "PIC16ISD::BTFSS"; case PIC16ISD::BTFSS : return "PIC16ISD::BTFSS";
case PIC16ISD::BTFSC : return "PIC16ISD::BTFSC"; case PIC16ISD::BTFSC : return "PIC16ISD::BTFSC";
case PIC16ISD::XORCC : return "PIC16ISD::XORCC"; case PIC16ISD::XORCC : return "PIC16ISD::XORCC";
@@ -56,97 +55,77 @@ const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
PIC16TargetLowering:: PIC16TargetLowering::
PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM) PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
{ {
// PIC16 does not have i1 type, so use i8 for // Set up the register classes.
// setcc operations results (slt, sgt, ...). addRegisterClass(MVT::i8, PIC16::CPURegsRegisterClass);
// setSetCCResultType(MVT::i8);
// setSetCCResultContents(ZeroOrOneSetCCResult);
// Set up the register classes
addRegisterClass(MVT::i8, PIC16::CPURegsRegisterClass);
addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass); addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass);
// Custom
// Load extented operations for i1 types must be promoted // Load extented operations for i1 types must be promoted .
setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
// Store operations for i1 types must be promoted setOperationAction(ISD::ADD, MVT::i1, Promote);
// setStoreXAction(MVT::i1, Promote); setOperationAction(ISD::ADD, MVT::i8, Legal);
// setStoreXAction(MVT::i8, Legal); setOperationAction(ISD::ADD, MVT::i16, Custom);
// setStoreXAction(MVT::i16, Custom); setOperationAction(ISD::ADD, MVT::i32, Expand);
// setStoreXAction(MVT::i32, Expand); setOperationAction(ISD::ADD, MVT::i64, Expand);
// setOperationAction(ISD::BUILD_PAIR, MVT::i32, Expand); setOperationAction(ISD::SUB, MVT::i1, Promote);
// setOperationAction(ISD::BUILD_PAIR, MVT::i16, Expand); setOperationAction(ISD::SUB, MVT::i8, Legal);
setOperationAction(ISD::SUB, MVT::i16, Custom);
setOperationAction(ISD::SUB, MVT::i32, Expand);
setOperationAction(ISD::SUB, MVT::i64, Expand);
setOperationAction(ISD::ADD, MVT::i1, Promote); setOperationAction(ISD::ADDC, MVT::i1, Promote);
setOperationAction(ISD::ADD, MVT::i8, Legal); setOperationAction(ISD::ADDC, MVT::i8, Legal);
setOperationAction(ISD::ADD, MVT::i16, Custom); setOperationAction(ISD::ADDC, MVT::i16, Custom);
setOperationAction(ISD::ADD, MVT::i32, Expand); setOperationAction(ISD::ADDC, MVT::i32, Expand);
setOperationAction(ISD::ADD, MVT::i64, Expand); setOperationAction(ISD::ADDC, MVT::i64, Expand);
setOperationAction(ISD::SUB, MVT::i1, Promote); setOperationAction(ISD::ADDE, MVT::i1, Promote);
setOperationAction(ISD::SUB, MVT::i8, Legal); setOperationAction(ISD::ADDE, MVT::i8, Legal);
setOperationAction(ISD::SUB, MVT::i16, Custom); setOperationAction(ISD::ADDE, MVT::i16, Custom);
setOperationAction(ISD::SUB, MVT::i32, Expand); setOperationAction(ISD::ADDE, MVT::i32, Expand);
setOperationAction(ISD::SUB, MVT::i64, Expand); setOperationAction(ISD::ADDE, MVT::i64, Expand);
setOperationAction(ISD::ADDC, MVT::i1, Promote); setOperationAction(ISD::SUBC, MVT::i1, Promote);
setOperationAction(ISD::ADDC, MVT::i8, Legal); setOperationAction(ISD::SUBC, MVT::i8, Legal);
setOperationAction(ISD::ADDC, MVT::i16, Custom); setOperationAction(ISD::SUBC, MVT::i16, Custom);
setOperationAction(ISD::ADDC, MVT::i32, Expand); setOperationAction(ISD::SUBC, MVT::i32, Expand);
setOperationAction(ISD::ADDC, MVT::i64, Expand); setOperationAction(ISD::SUBC, MVT::i64, Expand);
setOperationAction(ISD::ADDE, MVT::i1, Promote); setOperationAction(ISD::SUBE, MVT::i1, Promote);
setOperationAction(ISD::ADDE, MVT::i8, Legal); setOperationAction(ISD::SUBE, MVT::i8, Legal);
setOperationAction(ISD::ADDE, MVT::i16, Custom); setOperationAction(ISD::SUBE, MVT::i16, Custom);
setOperationAction(ISD::ADDE, MVT::i32, Expand); setOperationAction(ISD::SUBE, MVT::i32, Expand);
setOperationAction(ISD::ADDE, MVT::i64, Expand); setOperationAction(ISD::SUBE, MVT::i64, Expand);
setOperationAction(ISD::SUBC, MVT::i1, Promote);
setOperationAction(ISD::SUBC, MVT::i8, Legal);
setOperationAction(ISD::SUBC, MVT::i16, Custom);
setOperationAction(ISD::SUBC, MVT::i32, Expand);
setOperationAction(ISD::SUBC, MVT::i64, Expand);
setOperationAction(ISD::SUBE, MVT::i1, Promote);
setOperationAction(ISD::SUBE, MVT::i8, Legal);
setOperationAction(ISD::SUBE, MVT::i16, Custom);
setOperationAction(ISD::SUBE, MVT::i32, Expand);
setOperationAction(ISD::SUBE, MVT::i64, Expand);
// PIC16 does not have these NodeTypes below. // PIC16 does not have these NodeTypes below.
setOperationAction(ISD::SETCC, MVT::i1, Expand); setOperationAction(ISD::SETCC, MVT::i1, Expand);
setOperationAction(ISD::SETCC, MVT::i8, Expand); setOperationAction(ISD::SETCC, MVT::i8, Expand);
setOperationAction(ISD::SETCC, MVT::Other, Expand); setOperationAction(ISD::SETCC, MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i1, Custom); setOperationAction(ISD::SELECT_CC, MVT::i1, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
setOperationAction(ISD::BRCOND, MVT::i1, Expand); setOperationAction(ISD::BRCOND, MVT::i1, Expand);
setOperationAction(ISD::BRCOND, MVT::i8, Expand); setOperationAction(ISD::BRCOND, MVT::i8, Expand);
setOperationAction(ISD::BRCOND, MVT::Other, Expand); setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::i1, Custom);
setOperationAction(ISD::BR_CC, MVT::i8, Custom); setOperationAction(ISD::BR_CC, MVT::i1, Custom);
setOperationAction(ISD::BR_CC, MVT::i8, Custom);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Do we really need to Custom lower the GA ?? // FIXME: Do we really need to Custom lower the GA ??
// setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom); setOperationAction(ISD::RET, MVT::Other, Custom);
// PIC16 not supported intrinsics.
// setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
// setOperationAction(ISD::MEMSET, MVT::Other, Expand);
// setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ , MVT::i32, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ , MVT::i32, Expand); setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTR , MVT::i32, Expand); setOperationAction(ISD::ROTR, MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
@@ -158,14 +137,12 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand); setOperationAction(ISD::LABEL, MVT::Other, Expand);
// Use the default for now // Use the default for now.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::LOAD, MVT::i1, Promote); setOperationAction(ISD::LOAD, MVT::i1, Promote);
setOperationAction(ISD::LOAD, MVT::i8, Legal); setOperationAction(ISD::LOAD, MVT::i8, Legal);
// setOperationAction(ISD::LOAD, MVT::i16, Expand);
// setOperationAction(ISD::LOAD, MVT::i32, Expand);
setTargetDAGCombine(ISD::LOAD); setTargetDAGCombine(ISD::LOAD);
setTargetDAGCombine(ISD::STORE); setTargetDAGCombine(ISD::STORE);
@@ -176,11 +153,6 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
setTargetDAGCombine(ISD::SUBC); setTargetDAGCombine(ISD::SUBC);
setTargetDAGCombine(ISD::SUB); setTargetDAGCombine(ISD::SUB);
// We must find a way to get rid of Package nodes in the map
// setTargetDAGCombine(PIC16ISD::Package);
// getValueTypeActions().setTypeAction((MVT::ValueType)MVT::i16, Expand);
setStackPointerRegisterToSaveRestore(PIC16::STKPTR); setStackPointerRegisterToSaveRestore(PIC16::STKPTR);
computeRegisterProperties(); computeRegisterProperties();
} }
@@ -189,33 +161,39 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
{ {
SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other); SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
switch (Op.getOpcode()) switch (Op.getOpcode()) {
{
case ISD::STORE: case ISD::STORE:
cout << "reduce store\n"; DOUT << "reduce store\n";
break;
case ISD::FORMAL_ARGUMENTS:
cout<<"==== lowering formal args\n";
return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::GlobalAddress:
cout<<"==== lowering GA\n";
return LowerGlobalAddress(Op, DAG);
case ISD::RET:
cout<<"==== lowering ret\n";
return LowerRET(Op, DAG);
case ISD::FrameIndex:
cout<<"==== lowering frame index\n";
return LowerFrameIndex(Op, DAG);
case ISD::ADDE:
cout <<"==== lowering adde\n";
break; break;
case ISD::FORMAL_ARGUMENTS:
DOUT << "==== lowering formal args\n";
return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::GlobalAddress:
DOUT << "==== lowering GA\n";
return LowerGlobalAddress(Op, DAG);
case ISD::RET:
DOUT << "==== lowering ret\n";
return LowerRET(Op, DAG);
case ISD::FrameIndex:
DOUT << "==== lowering frame index\n";
return LowerFrameIndex(Op, DAG);
case ISD::ADDE:
DOUT << "==== lowering adde\n";
break;
case ISD::LOAD: case ISD::LOAD:
case ISD::ADD: case ISD::ADD:
break; break;
case ISD::BR_CC:
cout << "==== lowering BR_CC\n"; case ISD::BR_CC:
DOUT << "==== lowering BR_CC\n";
return LowerBR_CC(Op, DAG); return LowerBR_CC(Op, DAG);
} //end swithch } // end switch.
return SDOperand(); return SDOperand();
} }
@@ -224,9 +202,7 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
// Lower helper functions // Lower helper functions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
SDOperand
PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
{ {
MVT::ValueType VT = Op.getValueType(); MVT::ValueType VT = Op.getValueType();
SDOperand Chain = Op.getOperand(0); SDOperand Chain = Op.getOperand(0);
@@ -239,74 +215,66 @@ PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
unsigned branchOpcode; unsigned branchOpcode;
SDOperand branchOperand; SDOperand branchOperand;
SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG,MVT::i8); SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
SDOperand CPUReg = DAG.getRegister(PIC16::WREG,MVT::i8); SDOperand CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
switch(CC) switch(CC) {
{
default: default:
assert(0 && "This condition code is not handled yet!!"); assert(0 && "This condition code is not handled yet!!");
abort(); abort();
case ISD::SETNE: case ISD::SETNE:
{ DOUT << "setne\n";
cout << "setne\n";
cmpOpcode = PIC16ISD::XORCC; cmpOpcode = PIC16ISD::XORCC;
branchOpcode = PIC16ISD::BTFSS; branchOpcode = PIC16ISD::BTFSS;
branchOperand = DAG.getConstant(2,MVT::i8); branchOperand = DAG.getConstant(2, MVT::i8);
break; break;
}
case ISD::SETEQ: case ISD::SETEQ:
{ DOUT << "seteq\n";
cout << "seteq\n";
cmpOpcode = PIC16ISD::XORCC; cmpOpcode = PIC16ISD::XORCC;
branchOpcode = PIC16ISD::BTFSC; branchOpcode = PIC16ISD::BTFSC;
branchOperand = DAG.getConstant(2,MVT::i8); branchOperand = DAG.getConstant(2, MVT::i8);
break; break;
}
case ISD::SETGT: case ISD::SETGT:
{
assert(0 && "Greater Than condition code is not handled yet!!"); assert(0 && "Greater Than condition code is not handled yet!!");
abort(); abort();
} break;
case ISD::SETGE: case ISD::SETGE:
{ DOUT << "setge\n";
cout << "setge\n";
cmpOpcode = PIC16ISD::SUBCC; cmpOpcode = PIC16ISD::SUBCC;
branchOpcode = PIC16ISD::BTFSS; branchOpcode = PIC16ISD::BTFSS;
branchOperand = DAG.getConstant(1, MVT::i8); branchOperand = DAG.getConstant(1, MVT::i8);
break; break;
}
case ISD::SETLT: case ISD::SETLT:
{ DOUT << "setlt\n";
cout << "setlt\n";
cmpOpcode = PIC16ISD::SUBCC; cmpOpcode = PIC16ISD::SUBCC;
branchOpcode = PIC16ISD::BTFSC; branchOpcode = PIC16ISD::BTFSC;
branchOperand = DAG.getConstant(1,MVT::i8); branchOperand = DAG.getConstant(1,MVT::i8);
break; break;
}
case ISD::SETLE: case ISD::SETLE:
{
assert(0 && "Less Than Equal condition code is not handled yet!!"); assert(0 && "Less Than Equal condition code is not handled yet!!");
abort(); abort();
} break;
} // End of Switch } // End of Switch
SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag); SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1); SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
// SDOperand CCOper = DAG.getConstant(CC,MVT::i8);
// Result = DAG.getNode(branchOpcode,VT, Chain, JumpVal, CCOper, StatusReg,
// CmpValue);
Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand, Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand,
StatusReg, CmpValue); StatusReg, CmpValue);
return Result; return Result;
// return SDOperand();
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Misc Lower Operation implementation // Misc Lower Operation implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Create a constant pool entry for global value and wrap it in a wrapper node.
// LowerGlobalAddress - Create a constant pool entry for global value
// and wrap it in a wrapper node.
SDOperand SDOperand
PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
{ {
@@ -314,7 +282,7 @@ PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal(); GlobalValue *GV = GSDN->getGlobal();
//for now only do the ram. // FIXME: for now only do the ram.
SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr); SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank); CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
@@ -325,11 +293,11 @@ PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
SDOperand SDOperand
PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG)
{ {
switch(Op.getNumOperands()) switch(Op.getNumOperands()) {
{
default: default:
assert(0 && "Do not know how to return this many arguments!"); assert(0 && "Do not know how to return this many arguments!");
abort(); abort();
case 1: case 1:
return SDOperand(); // ret void is legal return SDOperand(); // ret void is legal
} }
@@ -360,8 +328,8 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
// If this load is directly stored, replace the load value with the stored // If this load is directly stored, replace the load value with the stored
// value. // value.
// TODO: Handle store large -> read small portion. // FIXME: Handle store large -> read small portion.
// TODO: Handle TRUNCSTORE/LOADEXT // FIXME: Handle TRUNCSTORE/LOADEXT
LoadSDNode *LD = cast<LoadSDNode>(N); LoadSDNode *LD = cast<LoadSDNode>(N);
SDOperand Ptr = LD->getBasePtr(); SDOperand Ptr = LD->getBasePtr();
if (LD->getExtensionType() == ISD::NON_EXTLOAD) { if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
@@ -381,7 +349,7 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src, toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
DAG.getConstant(1, MVT::i16)); DAG.getConstant(1, MVT::i16));
Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0); Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
// Add to worklist may not be needed. // FIXME: Add to worklist may not be needed.
// It is meant to merge sequences of add with constant into one. // It is meant to merge sequences of add with constant into one.
DCI.AddToWorklist(toWorklist.Val); DCI.AddToWorklist(toWorklist.Val);
@@ -405,7 +373,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
bool changed = false; bool changed = false;
int i; int i;
SDOperand LoOps[3], HiOps[3]; SDOperand LoOps[3], HiOps[3];
SDOperand OutOps[3]; //[0]:left, [1]:right, [2]:carry SDOperand OutOps[3]; // [0]:left, [1]:right, [2]:carry
SDOperand InOp[2]; SDOperand InOp[2];
SDOperand retVal; SDOperand retVal;
SDOperand as1,as2; SDOperand as1,as2;
@@ -415,8 +383,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
InOp[0] = N->getOperand(0); InOp[0] = N->getOperand(0);
InOp[1] = N->getOperand(1); InOp[1] = N->getOperand(1);
switch (N->getOpcode()) switch (N->getOpcode()) {
{
case ISD::ADD: case ISD::ADD:
if (InOp[0].getOpcode() == ISD::Constant && if (InOp[0].getOpcode() == ISD::Constant &&
InOp[1].getOpcode() == ISD::Constant) { InOp[1].getOpcode() == ISD::Constant) {
@@ -424,12 +391,15 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]); ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
return DAG.getConstant(CST0->getValue() + CST1->getValue(), MVT::i16); return DAG.getConstant(CST0->getValue() + CST1->getValue(), MVT::i16);
} }
break;
case ISD::ADDE: case ISD::ADDE:
case ISD::ADDC: case ISD::ADDC:
AS = ISD::ADD; AS = ISD::ADD;
ASE = ISD::ADDE; ASE = ISD::ADDE;
ASC = ISD::ADDC; ASC = ISD::ADDC;
break; break;
case ISD::SUB: case ISD::SUB:
if (InOp[0].getOpcode() == ISD::Constant && if (InOp[0].getOpcode() == ISD::Constant &&
InOp[1].getOpcode() == ISD::Constant) { InOp[1].getOpcode() == ISD::Constant) {
@@ -437,23 +407,25 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]); ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
return DAG.getConstant(CST0->getValue() - CST1->getValue(), MVT::i16); return DAG.getConstant(CST0->getValue() - CST1->getValue(), MVT::i16);
} }
break;
case ISD::SUBE: case ISD::SUBE:
case ISD::SUBC: case ISD::SUBC:
AS = ISD::SUB; AS = ISD::SUB;
ASE = ISD::SUBE; ASE = ISD::SUBE;
ASC = ISD::SUBC; ASC = ISD::SUBC;
break; break;
} } // end switch.
assert ((N->getValueType(0) == MVT::i16) assert ((N->getValueType(0) == MVT::i16)
&& "expecting an MVT::i16 node for lowering"); && "expecting an MVT::i16 node for lowering");
assert ((N->getOperand(0).getValueType() == MVT::i16) assert ((N->getOperand(0).getValueType() == MVT::i16)
&& (N->getOperand(1).getValueType() == MVT::i16) && (N->getOperand(1).getValueType() == MVT::i16)
&& "both inputs to addx/subx:i16 must be i16"); && "both inputs to addx/subx:i16 must be i16");
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
if (InOp[i].getOpcode() == ISD::GlobalAddress) { if (InOp[i].getOpcode() == ISD::GlobalAddress) {
//we don't want to lower subs/adds with global address (at least not yet) // We don't want to lower subs/adds with global address yet.
return SDOperand(); return SDOperand();
} }
else if (InOp[i].getOpcode() == ISD::Constant) { else if (InOp[i].getOpcode() == ISD::Constant) {
@@ -469,11 +441,11 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
else if (InOp[i].getOpcode() == ISD::LOAD) { else if (InOp[i].getOpcode() == ISD::LOAD) {
changed = true; changed = true;
// LowerLOAD returns a Package node or it may combine and return // LowerLOAD returns a Package node or it may combine and return
// anything else // anything else.
SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI); SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
// So If LowerLOAD returns something other than Package, // So If LowerLOAD returns something other than Package,
// then just call ADD again // then just call ADD again.
if (lowered.getOpcode() != PIC16ISD::Package) if (lowered.getOpcode() != PIC16ISD::Package)
return LowerADDSUB(N, DAG, DCI); return LowerADDSUB(N, DAG, DCI);
@@ -487,15 +459,15 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
(InOp[i].getOpcode() == ISD::SUBE) || (InOp[i].getOpcode() == ISD::SUBE) ||
(InOp[i].getOpcode() == ISD::SUBC)) { (InOp[i].getOpcode() == ISD::SUBC)) {
changed = true; changed = true;
//must call LowerADDSUB recursively here.... // Must call LowerADDSUB recursively here,
//LowerADDSUB returns a Package node // LowerADDSUB returns a Package node.
SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI); SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
LoOps[i] = lowered.getOperand(0); LoOps[i] = lowered.getOperand(0);
HiOps[i] = lowered.getOperand(1); HiOps[i] = lowered.getOperand(1);
} }
else if (InOp[i].getOpcode() == ISD::SIGN_EXTEND) { else if (InOp[i].getOpcode() == ISD::SIGN_EXTEND) {
//FIXME: I am just zero extending. for now. // FIXME: I am just zero extending. for now.
changed = true; changed = true;
LoOps[i] = InOp[i].getOperand(0); LoOps[i] = InOp[i].getOperand(0);
HiOps[i] = DAG.getConstant(0, MVT::i8); HiOps[i] = DAG.getConstant(0, MVT::i8);
@@ -505,14 +477,14 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
DAG.viewGraph(); DAG.viewGraph();
assert (0 && "not implemented yet"); assert (0 && "not implemented yet");
} }
} //end for } // end for.
assert (changed && "nothing changed while lowering SUBx/ADDx"); assert (changed && "nothing changed while lowering SUBx/ADDx");
VTList = DAG.getVTList(MVT::i8, MVT::Flag); VTList = DAG.getVTList(MVT::i8, MVT::Flag);
if (N->getOpcode() == ASE) { if (N->getOpcode() == ASE) {
//we must take in the existing carry // We must take in the existing carry
//if this node is part of an existing subx/addx sequence // if this node is part of an existing subx/addx sequence.
LoOps[2] = N->getOperand(2).getValue(1); LoOps[2] = N->getOperand(2).getValue(1);
as1 = DAG.getNode (ASE, VTList, LoOps, 3); as1 = DAG.getNode (ASE, VTList, LoOps, 3);
} }
@@ -521,11 +493,11 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
} }
HiOps[2] = as1.getValue(1); HiOps[2] = as1.getValue(1);
as2 = DAG.getNode (ASE, VTList, HiOps, 3); as2 = DAG.getNode (ASE, VTList, HiOps, 3);
//we must build a pair that also provides the carry from sube/adde // We must build a pair that also provides the carry from sube/adde.
OutOps[0] = as1; OutOps[0] = as1;
OutOps[1] = as2; OutOps[1] = as2;
OutOps[2] = as2.getValue(1); OutOps[2] = as2.getValue(1);
//breaking an original i16 so lets make the Package also an i16 // Breaking an original i16, so lets make the Package also an i16.
if (N->getOpcode() == ASE) { if (N->getOpcode() == ASE) {
VTList = DAG.getVTList(MVT::i16, MVT::Flag); VTList = DAG.getVTList(MVT::i16, MVT::Flag);
retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 3); retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 3);
@@ -548,13 +520,6 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Calling Convention Implementation // Calling Convention Implementation
//
// The lower operations present on calling convention works on this order:
// LowerCALL (virt regs --> phys regs, virt regs --> stack)
// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
// LowerRET (virt regs --> phys regs)
// LowerCALL (phys regs --> virt regs)
//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "PIC16GenCallingConv.inc" #include "PIC16GenCallingConv.inc"
@@ -574,7 +539,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
SDOperand Root = Op.getOperand(0); SDOperand Root = Op.getOperand(0);
// Return the new list of results. // Return the new list of results.
// Just copy right now. // FIXME: Just copy right now.
ArgValues.push_back(Root); ArgValues.push_back(Root);
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), &ArgValues[0], return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), &ArgValues[0],
@@ -601,184 +566,182 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
ConstantSDNode *CST; ConstantSDNode *CST;
SelectionDAG &DAG = DCI.DAG; SelectionDAG &DAG = DCI.DAG;
switch (N->getOpcode()) switch (N->getOpcode()) {
{ default:
default: break; break;
case PIC16ISD::Package :
cout <<"==== combining PIC16ISD::Package\n"; case PIC16ISD::Package:
return SDOperand(); DOUT << "==== combining PIC16ISD::Package\n";
case ISD::ADD :
case ISD::SUB :
if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
(N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
//do not touch pointer adds
return SDOperand ();
}
case ISD::ADDE :
case ISD::ADDC :
case ISD::SUBE :
case ISD::SUBC :
if (N->getValueType(0) == MVT::i16) {
SDOperand retVal = LowerADDSUB(N, DAG,DCI);
// LowerADDSUB has already combined the result,
// so we just return nothing to avoid assertion failure from llvm
// if N has been deleted already
return SDOperand(); return SDOperand();
}
else if (N->getValueType(0) == MVT::i8) { case ISD::ADD:
//sanity check .... case ISD::SUB:
for (int i=0; i<2; i++) { if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
if (N->getOperand (i).getOpcode() == PIC16ISD::Package) { (N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
assert (0 && // Do not touch pointer adds.
"don't want to have PIC16ISD::Package as intput to add:i8"); return SDOperand ();
}
break;
case ISD::ADDE :
case ISD::ADDC :
case ISD::SUBE :
case ISD::SUBC :
if (N->getValueType(0) == MVT::i16) {
SDOperand retVal = LowerADDSUB(N, DAG,DCI);
// LowerADDSUB has already combined the result,
// so we just return nothing to avoid assertion failure from llvm
// if N has been deleted already.
return SDOperand();
}
else if (N->getValueType(0) == MVT::i8) {
// Sanity check ....
for (int i=0; i<2; i++) {
if (N->getOperand (i).getOpcode() == PIC16ISD::Package) {
assert (0 &&
"don't want to have PIC16ISD::Package as intput to add:i8");
}
} }
} }
} break;
break;
case ISD::STORE :
{
SDOperand Chain = N->getOperand(0);
SDOperand Src = N->getOperand(1);
SDOperand Dest = N->getOperand(2);
unsigned int DstOff = 0;
int NUM_STORES;
SDOperand Stores[6];
// FIXME: split this large chunk of code.
// if source operand is expected to be extended to case ISD::STORE :
// some higher type then - remove this extension
// SDNode and do the extension manually
if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
(Src.getOpcode() == ISD::SIGN_EXTEND) ||
(Src.getOpcode() == ISD::ZERO_EXTEND)) {
Src = Src.Val->getOperand(0);
Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
return Stores[0];
}
switch(Src.getValueType())
{ {
case MVT::i8: SDOperand Chain = N->getOperand(0);
break; SDOperand Src = N->getOperand(1);
case MVT::i16: SDOperand Dest = N->getOperand(2);
NUM_STORES = 2; unsigned int DstOff = 0;
break; int NUM_STORES;
case MVT::i32: SDOperand Stores[6];
NUM_STORES = 4;
break;
case MVT::i64:
NUM_STORES = 8;
break;
}
if (isa<GlobalAddressSDNode>(Dest) && isa<LoadSDNode>(Src) && // if source operand is expected to be extended to
(Src.getValueType() != MVT::i8)) { // some higher type then - remove this extension
//create direct addressing a = b // SDNode and do the extension manually
Chain = Src.getOperand(0); if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
for (i=0; i<NUM_STORES; i++) { (Src.getOpcode() == ISD::SIGN_EXTEND) ||
SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1), (Src.getOpcode() == ISD::ZERO_EXTEND)) {
DAG.getConstant(DstOff, MVT::i16)); Src = Src.Val->getOperand(0);
SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0); Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest, return Stores[0];
DAG.getConstant(DstOff, MVT::i16)); }
Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
Chain = Stores[i]; switch(Src.getValueType()) {
DstOff += 1; case MVT::i8:
} break;
case MVT::i16:
NUM_STORES = 2;
break;
case MVT::i32:
NUM_STORES = 4;
break;
case MVT::i64:
NUM_STORES = 8;
break;
}
if (isa<GlobalAddressSDNode>(Dest) && isa<LoadSDNode>(Src) &&
(Src.getValueType() != MVT::i8)) {
//create direct addressing a = b
Chain = Src.getOperand(0);
for (i=0; i<NUM_STORES; i++) {
SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
DAG.getConstant(DstOff, MVT::i16));
SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(DstOff, MVT::i16));
Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
Chain = Stores[i];
DstOff += 1;
}
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i); Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
return Chain; return Chain;
} }
else if (isa<GlobalAddressSDNode>(Dest) && isa<ConstantSDNode>(Src) else if (isa<GlobalAddressSDNode>(Dest) && isa<ConstantSDNode>(Src)
&& (Src.getValueType() != MVT::i8)) && (Src.getValueType() != MVT::i8)) {
{ //create direct addressing a = CONST
//create direct addressing a = CONST CST = dyn_cast<ConstantSDNode>(Src);
CST = dyn_cast<ConstantSDNode>(Src); for (i = 0; i < NUM_STORES; i++) {
for (i = 0; i < NUM_STORES; i++) { SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8); SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest, DAG.getConstant(DstOff, MVT::i16));
DAG.getConstant(DstOff, MVT::i16)); Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0); Chain = Stores[i];
Chain = Stores[i]; DstOff += 1;
DstOff += 1; }
}
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i); Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
return Chain; return Chain;
} }
else if (isa<LoadSDNode>(Dest) && isa<ConstantSDNode>(Src) else if (isa<LoadSDNode>(Dest) && isa<ConstantSDNode>(Src)
&& (Src.getValueType() != MVT::i8)) { && (Src.getValueType() != MVT::i8)) {
//create indirect addressing // Create indirect addressing.
CST = dyn_cast<ConstantSDNode>(Src); CST = dyn_cast<ConstantSDNode>(Src);
Chain = Dest.getOperand(0); Chain = Dest.getOperand(0);
SDOperand Load; SDOperand Load;
Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0); Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
Chain = Load.getValue(1); Chain = Load.getValue(1);
for (i=0; i<NUM_STORES; i++) { for (i=0; i<NUM_STORES; i++) {
SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8); SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0); Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
Chain = Stores[i]; Chain = Stores[i];
DstOff += 1; DstOff += 1;
} }
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i); Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
return Chain; return Chain;
} }
else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) { else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) {
// GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src); // GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src);
return SDOperand(); return SDOperand();
} }
else if (Src.getOpcode() == PIC16ISD::Package) { else if (Src.getOpcode() == PIC16ISD::Package) {
StoreSDNode *st = dyn_cast<StoreSDNode>(N); StoreSDNode *st = dyn_cast<StoreSDNode>(N);
SDOperand toWorkList, retVal; SDOperand toWorkList, retVal;
Chain = N->getOperand(0); Chain = N->getOperand(0);
if (st->isTruncatingStore()) { if (st->isTruncatingStore()) {
retVal = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0); retVal = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
}
else {
toWorkList = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(1, MVT::i16));
Stores[1] = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL,
0);
// We want to merge sequence of add with constant to one add and a
// constant, so add the ADD node to worklist to have llvm do that
// automatically.
DCI.AddToWorklist(toWorkList.Val);
// We don't need the Package so add to worklist so llvm deletes it
DCI.AddToWorklist(Src.Val);
retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
}
return retVal;
}
else if (Src.getOpcode() == ISD::TRUNCATE) {
} }
else { else {
toWorkList = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(1, MVT::i16));
Stores[1] = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL, 0);
// We want to merge sequence of add with constant to one add and a
// constant, so add the ADD node to worklist to have llvm do that
// automatically.
DCI.AddToWorklist(toWorkList.Val);
// We don't need the Package so add to worklist so llvm deletes it
DCI.AddToWorklist(Src.Val);
retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
} }
} // end ISD::STORE.
break;
return retVal; case ISD::LOAD :
{
SDOperand Ptr = N->getOperand(1);
if (Ptr.getOpcode() == PIC16ISD::Package) {
assert (0 && "not implemented yet");
}
} }
else if (Src.getOpcode() == ISD::TRUNCATE) { break;
} } // end switch.
else {
// DAG.setGraphColor(N, "blue");
// DAG.viewGraph();
// assert (0 && "input to store not implemented yet");
}
} //end ISD::STORE
break;
case ISD::LOAD :
{
SDOperand Ptr = N->getOperand(1);
if (Ptr.getOpcode() == PIC16ISD::Package) {
// DAG.setGraphColor(N, "blue");
// DAG.viewGraph();
// Here we must make so that:
// Ptr.getOperand(0) --> fsrl
// Ptr.getOperand(1) --> fsrh
assert (0 && "not implemented yet");
}
//return SDOperand();
//break;
}
}//end switch
return SDOperand(); return SDOperand();
} }
@@ -793,8 +756,8 @@ findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const
if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8)) if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8))
return &Src; return &Src;
for (i=0; i<Src.getNumOperands(); i++) { for (i=0; i<Src.getNumOperands(); i++) {
const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG); const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG);
if (retVal) return retVal; if (retVal) return retVal;
} }
return NULL; return NULL;

20
lib/Target/PIC16/PIC16ISelLowering.h
View File

@@ -15,10 +15,10 @@
#ifndef PIC16ISELLOWERING_H #ifndef PIC16ISELLOWERING_H
#define PIC16ISELLOWERING_H #define PIC16ISELLOWERING_H
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetLowering.h"
#include "PIC16.h" #include "PIC16.h"
#include "PIC16Subtarget.h" #include "PIC16Subtarget.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm { namespace llvm {
namespace PIC16ISD { namespace PIC16ISD {
@@ -35,15 +35,15 @@ namespace llvm {
// Get the Lower 16 bits from a 32-bit immediate // Get the Lower 16 bits from a 32-bit immediate
Lo, Lo,
Cmp, // PIC16 Generic Comparison instruction. Cmp, // PIC16 Generic Comparison instruction.
Branch, // PIC16 Generic Branch Instruction. Branch, // PIC16 Generic Branch Instruction.
BTFSS, // PIC16 BitTest Instruction (Skip if set). BTFSS, // PIC16 BitTest Instruction (Skip if set).
BTFSC, // PIC16 BitTest Instruction (Skip if clear). BTFSC, // PIC16 BitTest Instruction (Skip if clear).
// PIC16 comparison to be converted to either XOR or SUB // PIC16 comparison to be converted to either XOR or SUB
// Following instructions cater to those convertions. // Following instructions cater to those convertions.
XORCC, XORCC,
SUBCC, SUBCC,
// Get the Global Address wrapped into a wrapper that also captures // Get the Global Address wrapped into a wrapper that also captures
// the bank or page. // the bank or page.
@@ -73,9 +73,9 @@ namespace llvm {
SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG); SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG);
SDOperand RemoveHiLo(SDNode *, SelectionDAG &DAG, SDOperand RemoveHiLo(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const; DAGCombinerInfo &DCI) const;
SDOperand LowerADDSUB(SDNode *, SelectionDAG &DAG, SDOperand LowerADDSUB(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const; DAGCombinerInfo &DCI) const;
SDOperand LowerLOAD(SDNode *, SelectionDAG &DAG, SDOperand LowerLOAD(SDNode *, SelectionDAG &DAG,
DAGCombinerInfo &DCI) const; DAGCombinerInfo &DCI) const;

20
lib/Target/PIC16/PIC16InstrFormats.td
View File

@@ -22,17 +22,17 @@
// Generic PIC16 Format // Generic PIC16 Format
class PIC16Inst<dag outs, dag ins, string asmstr, list<dag> pattern> class PIC16Inst<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction : Instruction
{ {
field bits<14> Inst; field bits<14> Inst;
let Namespace = "PIC16"; let Namespace = "PIC16";
dag OutOperandList = outs; dag OutOperandList = outs;
dag InOperandList = ins; dag InOperandList = ins;
let AsmString = asmstr; let AsmString = asmstr;
let Pattern = pattern; let Pattern = pattern;
} }
@@ -41,8 +41,8 @@ class PIC16Inst<dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ByteFormat<bits<6> op, dag outs, dag ins, string asmstr, class ByteFormat<bits<6> op, dag outs, dag ins, string asmstr,
list<dag> pattern> list<dag> pattern>
:PIC16Inst<outs, ins, asmstr, pattern> :PIC16Inst<outs, ins, asmstr, pattern>
{ {
bits<1> d; bits<1> d;
bits<7> f; bits<7> f;
@@ -74,8 +74,8 @@ class BitFormat<bits<4> op, dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class LiteralFormat<bits<6> op, dag outs, dag ins, string asmstr, class LiteralFormat<bits<6> op, dag outs, dag ins, string asmstr,
list<dag> pattern> list<dag> pattern>
: PIC16Inst<outs, ins, asmstr, pattern> : PIC16Inst<outs, ins, asmstr, pattern>
{ {
bits<8> k; bits<8> k;
@@ -90,8 +90,8 @@ class LiteralFormat<bits<6> op, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ControlFormat<bits<3> op, dag outs, dag ins, string asmstr, class ControlFormat<bits<3> op, dag outs, dag ins, string asmstr,
list<dag> pattern> list<dag> pattern>
:PIC16Inst<outs, ins, asmstr, pattern> :PIC16Inst<outs, ins, asmstr, pattern>
{ {
bits<11> k; bits<11> k;

8
lib/Target/PIC16/PIC16InstrInfo.cpp
View File

@@ -21,7 +21,7 @@
using namespace llvm; using namespace llvm;
// TODO: Add the subtarget support on this constructor. // FIXME: Add the subtarget support on this constructor.
PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm) PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
: TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)), : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
TM(tm), RI(*this) {} TM(tm), RI(*this) {}
@@ -87,7 +87,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB,
.addReg(SrcReg,false,false,true,true) .addReg(SrcReg,false,false,true,true)
.addExternalSymbol(tmpName) // the current printer expects 3 operands, .addExternalSymbol(tmpName) // the current printer expects 3 operands,
.addExternalSymbol(tmpName); // all we need is actually one, .addExternalSymbol(tmpName); // all we need is actually one,
// so we repeat. // so we repeat.
} }
else else
assert(0 && "Can't store this register to stack slot"); assert(0 && "Can't store this register to stack slot");
@@ -120,7 +120,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
/// instructions inserted. /// instructions inserted.
unsigned PIC16InstrInfo:: unsigned PIC16InstrInfo::
InsertBranch(MachineBasicBlock &MBB, InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const const std::vector<MachineOperand> &Cond) const
{ {
// Shouldn't be a fall through. // Shouldn't be a fall through.
@@ -134,7 +134,7 @@ InsertBranch(MachineBasicBlock &MBB,
return 1; return 1;
} }
// TODO: If the there are some conditions specified then conditional branch // FIXME: If the there are some conditions specified then conditional branch
// should be generated. // should be generated.
// For the time being no instruction is being generated therefore // For the time being no instruction is being generated therefore
// returning NULL. // returning NULL.

76
lib/Target/PIC16/PIC16InstrInfo.td
View File

@@ -46,7 +46,7 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PIC16CallSeq,
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PIC16CallSeq, def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PIC16CallSeq,
[SDNPHasChain, SDNPOutFlag]>; [SDNPHasChain, SDNPOutFlag]>;
def PIC16Wrapper : SDNode<"PIC16ISD::Wrapper", SDTIntUnaryOp>; def PIC16Wrapper : SDNode<"PIC16ISD::Wrapper", SDTIntUnaryOp>;
// so_imm_XFORM - Return a so_imm value packed into the format described for // so_imm_XFORM - Return a so_imm value packed into the format described for
// so_imm def below. // so_imm def below.
@@ -74,7 +74,7 @@ class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
!strconcat(instr_asm, " $c"), !strconcat(instr_asm, " $c"),
[(set CPURegs:$dst, (OpNode CPURegs:$b, Od:$c))]>; [(set CPURegs:$dst, (OpNode CPURegs:$b, Od:$c))]>;
// Memory Load/Store // Memory Load/Store.
class LoadDirect<bits<6> op, string instr_asm, PatFrag OpNode>: class LoadDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
ByteFormat< op, ByteFormat< op,
(outs CPURegs:$dst), (outs CPURegs:$dst),
@@ -103,7 +103,7 @@ class StoreInDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
!strconcat(instr_asm, " $fsr"), !strconcat(instr_asm, " $fsr"),
[(OpNode CPURegs:$src, PTRRegs:$fsr)]>; [(OpNode CPURegs:$src, PTRRegs:$fsr)]>;
// Move // Move.
class MovLit<bits<6> op, string instr_asm>: class MovLit<bits<6> op, string instr_asm>:
LiteralFormat< op, LiteralFormat< op,
(outs CPURegs:$dst), (outs CPURegs:$dst),
@@ -162,52 +162,52 @@ def MOVLW : MovLit<0x24, "movlw">;
} }
// Load/Store // Load/Store
def LFSR1 : LoadInDirect <0x4, "lfsr", load>; def LFSR1 : LoadInDirect <0x4, "lfsr", load>;
let isReMaterializable = 1 in { let isReMaterializable = 1 in {
def MOVF : LoadDirect <0x23, "movf", load>; def MOVF : LoadDirect <0x23, "movf", load>;
} }
def MOVWF : StoreDirect <0x2b, "movwf", store>; def MOVWF : StoreDirect <0x2b, "movwf", store>;
def MOVFSRINC : StoreInDirect <0x5, "movfsrinc", store>; def MOVFSRINC : StoreInDirect <0x5, "movfsrinc", store>;
def RETURN : ControlFormat<0x03, (outs), (ins), "return", []>; def RETURN : ControlFormat<0x03, (outs), (ins), "return", []>;
def ADDWF : Arith1M<0x01, "addwf", add>; def ADDWF : Arith1M<0x01, "addwf", add>;
def ADDFW : Arith1R<0x02, "addfw", add>; def ADDFW : Arith1R<0x02, "addfw", add>;
def ADDWFE : Arith1M<0x03, "addwfe", adde>; def ADDWFE : Arith1M<0x03, "addwfe", adde>;
def ADDFWE : Arith1R<0x04, "addfwe", adde>; def ADDFWE : Arith1R<0x04, "addfwe", adde>;
def ADDWFC : Arith1M<0x05, "addwfc", addc>; def ADDWFC : Arith1M<0x05, "addwfc", addc>;
def ADDFWC : Arith1R<0x06, "addfwc", addc>; def ADDFWC : Arith1R<0x06, "addfwc", addc>;
def SUBWF : Arith1M<0x07, "subwf", sub>; def SUBWF : Arith1M<0x07, "subwf", sub>;
def SUBFW : Arith1R<0x08, "subfw", sub>; def SUBFW : Arith1R<0x08, "subfw", sub>;
def SUBWFE : Arith1M<0x09, "subwfe", sube>; def SUBWFE : Arith1M<0x09, "subwfe", sube>;
def SUBFWE : Arith1R<0x0a, "subfwe", sube>; def SUBFWE : Arith1R<0x0a, "subfwe", sube>;
def SUBWFC : Arith1M<0x0b, "subwfc", subc>; def SUBWFC : Arith1M<0x0b, "subwfc", subc>;
def SUBFWC : Arith1R<0x0d, "subfwc", subc>; def SUBFWC : Arith1R<0x0d, "subfwc", subc>;
def SUBRFW : Arith2R<0x08, "subfw", sub>; def SUBRFW : Arith2R<0x08, "subfw", sub>;
def SUBRFWE : Arith2R<0x0a, "subfwe", sube>; def SUBRFWE : Arith2R<0x0a, "subfwe", sube>;
def SUBRFWC : Arith2R<0x0d, "subfwc", subc>; def SUBRFWC : Arith2R<0x0d, "subfwc", subc>;
def brtarget : Operand<OtherVT>; def brtarget : Operand<OtherVT>;
class UncondJump< bits<4> op, string instr_asm>: class UncondJump< bits<4> op, string instr_asm>:
BitFormat< op, BitFormat< op,
(outs), (outs),
(ins brtarget:$target), (ins brtarget:$target),
!strconcat(instr_asm, " $target"), !strconcat(instr_asm, " $target"),
[(br bb:$target)]>; [(br bb:$target)]>;
def GOTO : UncondJump<0x1, "goto">; def GOTO : UncondJump<0x1, "goto">;
class LogicM<bits<6> op, string instr_asm, SDNode OpNode> : class LogicM<bits<6> op, string instr_asm, SDNode OpNode> :
ByteFormat< op, ByteFormat< op,
@@ -246,7 +246,7 @@ def IORLW : LogicI<0x1,"iorlw",or, so_imm>;
/* For comparison before branch */ /* For comparison before branch */
def SDT_PIC16Cmp : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>]>; def SDT_PIC16Cmp : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>]>;
def SDTIntBinOpPIC16 : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, def SDTIntBinOpPIC16 : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
SDTCisSameAs<1,2>, SDTCisInt<1>]>; SDTCisSameAs<1,2>, SDTCisInt<1>]>;
def PIC16Cmp : SDNode<"PIC16ISD::Cmp",SDTIntBinOpPIC16, [SDNPOutFlag]>; def PIC16Cmp : SDNode<"PIC16ISD::Cmp",SDTIntBinOpPIC16, [SDNPOutFlag]>;
def PIC16XORCC : SDNode<"PIC16ISD::XORCC",SDTIntBinOpPIC16, [SDNPOutFlag]>; def PIC16XORCC : SDNode<"PIC16ISD::XORCC",SDTIntBinOpPIC16, [SDNPOutFlag]>;
@@ -260,23 +260,23 @@ def SUBLWCC : ArithI<0x1,"sublw",PIC16SUBCC, so_imm>;
/* For branch conditions */ /* For branch conditions */
def SDT_PIC16Branch : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, def SDT_PIC16Branch : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
SDTCisVT<1,i8>, SDTCisVT<2,i8>]>; SDTCisVT<1,i8>, SDTCisVT<2,i8>]>;
def PIC16Branch : SDNode<"PIC16ISD::Branch",SDT_PIC16Branch, def PIC16Branch : SDNode<"PIC16ISD::Branch",SDT_PIC16Branch,
[SDNPHasChain, SDNPInFlag]>; [SDNPHasChain, SDNPInFlag]>;
def PIC16BTFSS : SDNode<"PIC16ISD::BTFSS",SDT_PIC16Branch, def PIC16BTFSS : SDNode<"PIC16ISD::BTFSS",SDT_PIC16Branch,
[SDNPHasChain, SDNPInFlag]>; [SDNPHasChain, SDNPInFlag]>;
def PIC16BTFSC : SDNode<"PIC16ISD::BTFSC",SDT_PIC16Branch, def PIC16BTFSC : SDNode<"PIC16ISD::BTFSC",SDT_PIC16Branch,
[SDNPHasChain, SDNPInFlag]>; [SDNPHasChain, SDNPInFlag]>;
class InstrBitTestCC<bits<4> op, string instr_asm,SDNode OpNode>: class InstrBitTestCC<bits<4> op, string instr_asm,SDNode OpNode>:
BitFormat< op, BitFormat< op,
(outs), (outs),
(ins brtarget:$target ,so_imm:$i, STATUSRegs:$s ), (ins brtarget:$target ,so_imm:$i, STATUSRegs:$s ),
!strconcat(instr_asm, " $s, $i, $target"), !strconcat(instr_asm, " $s, $i, $target"),
[(OpNode bb:$target, so_imm:$i, STATUSRegs:$s )]>; [(OpNode bb:$target, so_imm:$i, STATUSRegs:$s )]>;
def BTFSS : InstrBitTestCC<0x1,"btfss",PIC16BTFSS>; def BTFSS : InstrBitTestCC<0x1,"btfss",PIC16BTFSS>;
def BTFSC : InstrBitTestCC<0x1,"btfsc",PIC16BTFSC>; def BTFSC : InstrBitTestCC<0x1,"btfsc",PIC16BTFSC>;

27
lib/Target/PIC16/PIC16RegisterInfo.cpp
View File

@@ -34,7 +34,7 @@
using namespace llvm; using namespace llvm;
// TODO: add subtarget support // FIXME: add subtarget support.
PIC16RegisterInfo::PIC16RegisterInfo(const TargetInstrInfo &tii) PIC16RegisterInfo::PIC16RegisterInfo(const TargetInstrInfo &tii)
: PIC16GenRegisterInfo(PIC16::ADJCALLSTACKDOWN, PIC16::ADJCALLSTACKUP), : PIC16GenRegisterInfo(PIC16::ADJCALLSTACKDOWN, PIC16::ADJCALLSTACKUP),
TII(tii) {} TII(tii) {}
@@ -44,8 +44,8 @@ PIC16RegisterInfo::PIC16RegisterInfo(const TargetInstrInfo &tii)
unsigned PIC16RegisterInfo:: unsigned PIC16RegisterInfo::
getRegisterNumbering(unsigned RegEnum) getRegisterNumbering(unsigned RegEnum)
{ {
assert (RegEnum <= 31 && "Unknown register number!"); assert (RegEnum <= 31 && "Unknown register number!");
return RegEnum; return RegEnum;
} }
void PIC16RegisterInfo:: void PIC16RegisterInfo::
@@ -61,16 +61,15 @@ void PIC16RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
unsigned DestReg, unsigned DestReg,
const MachineInstr *Orig) const const MachineInstr *Orig) const
{ {
MachineInstr *MI = Orig->clone(); MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg); MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI); MBB.insert(I, MI);
} }
MachineInstr *PIC16RegisterInfo:: MachineInstr *PIC16RegisterInfo::
foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
{ {
MachineInstr *NewMI = NULL; MachineInstr *NewMI = NULL;
return NewMI; return NewMI;
} }
@@ -152,27 +151,24 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
int stackSize = MF.getFrameInfo()->getStackSize(); int stackSize = MF.getFrameInfo()->getStackSize();
int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
#ifndef NDEBUG
DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n"; DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
DOUT << "<--------->\n"; DOUT << "<--------->\n";
#ifndef NDEBUG
MI.print(DOUT); MI.print(DOUT);
#endif
DOUT << "FrameIndex : " << FrameIndex << "\n"; DOUT << "FrameIndex : " << FrameIndex << "\n";
DOUT << "spOffset : " << spOffset << "\n"; DOUT << "spOffset : " << spOffset << "\n";
DOUT << "stackSize : " << stackSize << "\n"; DOUT << "stackSize : " << stackSize << "\n";
#endif
// as explained on LowerFORMAL_ARGUMENTS, detect negative offsets // As explained on LowerFORMAL_ARGUMENTS, detect negative offsets
// and adjust SPOffsets considering the final stack size. // and adjust SPOffsets considering the final stack size.
int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset)); int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
//Offset += MI.getOperand(i+1).getImm();
#ifndef NDEBUG
DOUT << "Offset : " << Offset << "\n"; DOUT << "Offset : " << Offset << "\n";
DOUT << "<--------->\n"; DOUT << "<--------->\n";
#endif
// MI.getOperand(i+1).ChangeToImmediate(Offset); // MI.getOperand(i+1).ChangeToImmediate(Offset);
MI.getOperand(i).ChangeToRegister(getFrameRegister(MF),false); MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
} }
void PIC16RegisterInfo:: void PIC16RegisterInfo::
@@ -186,7 +182,8 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
} }
void PIC16RegisterInfo:: void PIC16RegisterInfo::
processFunctionBeforeFrameFinalized(MachineFunction &MF) const { processFunctionBeforeFrameFinalized(MachineFunction &MF) const
{
} }
unsigned PIC16RegisterInfo:: unsigned PIC16RegisterInfo::

4
lib/Target/PIC16/PIC16RegisterInfo.h
View File

@@ -44,8 +44,8 @@ struct PIC16RegisterInfo : public PIC16GenRegisterInfo {
} }
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;

4
lib/Target/PIC16/PIC16Subtarget.cpp
View File

@@ -11,13 +11,13 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "PIC16Subtarget.h"
#include "PIC16.h" #include "PIC16.h"
#include "PIC16Subtarget.h"
#include "PIC16GenSubtarget.inc" #include "PIC16GenSubtarget.inc"
using namespace llvm; using namespace llvm;
PIC16Subtarget::PIC16Subtarget(const TargetMachine &TM, const Module &M, PIC16Subtarget::PIC16Subtarget(const TargetMachine &TM, const Module &M,
const std::string &FS) const std::string &FS)
:IsPIC16Old(false) :IsPIC16Old(false)
{ {
std::string CPU = "generic"; std::string CPU = "generic";

4
lib/Target/PIC16/PIC16Subtarget.h
View File

@@ -14,8 +14,8 @@
#ifndef PIC16SUBTARGET_H #ifndef PIC16SUBTARGET_H
#define PIC16SUBTARGET_H #define PIC16SUBTARGET_H
#include "llvm/Target/TargetSubtarget.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtarget.h"
#include <string> #include <string>
@@ -30,7 +30,7 @@ public:
/// of the specified module. /// of the specified module.
/// ///
PIC16Subtarget(const TargetMachine &TM, const Module &M, PIC16Subtarget(const TargetMachine &TM, const Module &M,
const std::string &FS); const std::string &FS);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.

12
lib/Target/PIC16/PIC16TargetMachine.cpp
View File

@@ -12,12 +12,12 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "PIC16.h" #include "PIC16.h"
#include "PIC16TargetMachine.h"
#include "PIC16TargetAsmInfo.h" #include "PIC16TargetAsmInfo.h"
#include "PIC16TargetMachine.h"
#include "llvm/Module.h" #include "llvm/Module.h"
#include "llvm/PassManager.h" #include "llvm/PassManager.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetMachineRegistry.h"
using namespace llvm; using namespace llvm;
@@ -33,8 +33,7 @@ PIC16TargetMachine(const Module &M, const std::string &FS) :
FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0) { } FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0) { }
const TargetAsmInfo *PIC16TargetMachine:: const TargetAsmInfo *PIC16TargetMachine::createTargetAsmInfo() const
createTargetAsmInfo() const
{ {
return new PIC16TargetAsmInfo(*this); return new PIC16TargetAsmInfo(*this);
} }
@@ -43,8 +42,7 @@ createTargetAsmInfo() const
// Pass Pipeline Configuration // Pass Pipeline Configuration
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
bool PIC16TargetMachine:: bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
addInstSelector(PassManagerBase &PM, bool Fast)
{ {
// Install an instruction selector. // Install an instruction selector.
PM.add(createPIC16ISelDag(*this)); PM.add(createPIC16ISelDag(*this));
@@ -57,7 +55,7 @@ addPrologEpilogInserter(PassManagerBase &PM, bool Fast)
return false; return false;
} }
bool PIC16TargetMachine:: addPreEmitPass(PassManagerBase &PM, bool Fast) bool PIC16TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast)
{ {
return true; return true;
} }

2
lib/Target/PIC16/PIC16TargetMachine.h
View File

@@ -54,7 +54,7 @@ public:
virtual bool addPrologEpilogInserter(PassManagerBase &PM, bool Fast); virtual bool addPrologEpilogInserter(PassManagerBase &PM, bool Fast);
virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
std::ostream &Out); std::ostream &Out);
}; };
} // end namespace llvm } // end namespace llvm