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Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
value that the one in ARMMCCodeEmitter.cpp does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -228,9 +228,9 @@ namespace {
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uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
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{ return 0; }
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uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
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// {12-9} = reg
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// {8} = (U)nsigned (add == '1', sub == '0')
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// {7-0} = imm12
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// {17-13} = reg
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// {12} = (U)nsigned (add == '1', sub == '0')
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// {11-0} = imm12
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const MachineOperand &MO = MI.getOperand(Op);
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const MachineOperand &MO1 = MI.getOperand(Op + 1);
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if (!MO.isReg()) {
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@ -238,12 +238,24 @@ namespace {
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return 0;
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}
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unsigned Reg = getARMRegisterNumbering(MO.getReg());
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int32_t Imm8 = MO1.getImm();
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uint32_t Binary;
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Binary = Imm8 & 0xff;
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if (Imm8 >= 0)
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Binary |= (1 << 8);
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Binary |= (Reg << 9);
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int32_t Imm12 = MO1.getImm();
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// Special value for #-0
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if (Imm12 == INT32_MIN)
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Imm12 = 0;
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// Immediate is always encoded as positive. The 'U' bit controls add vs
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// sub.
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bool isAdd = true;
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if (Imm12 < 0) {
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Imm12 = -Imm12;
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isAdd = false;
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}
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uint32_t Binary = Imm12 & 0xfff;
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if (isAdd)
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Binary |= (1 << 12);
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Binary |= (Reg << 13);
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return Binary;
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}
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unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
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