6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Add a new bit that ImmLeaf's can opt into, which allows them to duck out of

Browse Source 
the generated FastISel.  X86 doesn't need to generate code to match ADD16ri8 
since ADD16ri will do just fine.  This is a small codesize win in the generated
instruction selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2011-04-18 06:36:55 +00:00
parent 1518afddea
commit 202a7a1e3f
3 changed files with 23 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/Target/TargetSelectionDAG.td
View File

@@ -539,8 +539,14 @@ class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
// this is a more convenient form to match 'imm' nodes in than PatLeaf and also
// is preferred over using PatLeaf because it allows the code generator to
// reason more about the constraint.
class ImmLeaf<ValueType vt, code pred> : PatFrag<(ops), (vt imm)> {
//
// If FastIsel should ignore all instructions that have an operand of this type,
// the FastIselShouldIgnore flag can be set. This is an optimization to reduce
// the code size of the generated fast instruction selector.
class ImmLeaf<ValueType vt, code pred>
: PatFrag<(ops), (vt imm)> {
let ImmediateCode = pred;
bit FastIselShouldIgnore = 0;
}