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Add a new bit that ImmLeaf's can opt into, which allows them to duck out of

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the generated FastISel.  X86 doesn't need to generate code to match ADD16ri8 
since ADD16ri will do just fine.  This is a small codesize win in the generated
instruction selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2011-04-18 06:36:55 +00:00
parent 1518afddea
commit 202a7a1e3f
3 changed files with 23 additions and 6 deletions
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utils/TableGen/FastISelEmitter.cpp
+10 -2
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@@ -190,14 +190,22 @@ struct OperandsSignature {
if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
unsigned PredNo = 0;
if (!Op->getPredicateFns().empty()) {
TreePredicateFn PredFn = Op->getPredicateFns()[0];
// If there is more than one predicate weighing in on this operand
// then we don't handle it. This doesn't typically happen for
// immediates anyway.
if (Op->getPredicateFns().size() > 1 ||
!Op->getPredicateFns()[0].isImmediatePattern())
!PredFn.isImmediatePattern())
return false;
// Ignore any instruction with 'FastIselShouldIgnore', these are
// not needed and just bloat the fast instruction selector. For
// example, X86 doesn't need to generate code to match ADD16ri8 since
// ADD16ri will do just fine.
Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
if (Rec->getValueAsBit("FastIselShouldIgnore"))
return false;
PredNo = ImmediatePredicates.getIDFor(Op->getPredicateFns()[0])+1;
PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
}
// Handle unmatched immediate sizes here.