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Rename SelectionDAGLowering to SelectionDAGBuilder, and rename
SelectionDAGBuild.cpp to SelectionDAGBuilder.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89681 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
131c4a5257
commit
2048b85c7c
@ -23,7 +23,7 @@
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namespace llvm {
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class FastISel;
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class SelectionDAGLowering;
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class SelectionDAGBuilder;
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class SDValue;
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class MachineRegisterInfo;
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class MachineBasicBlock;
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@ -48,7 +48,7 @@ public:
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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SelectionDAG *CurDAG;
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SelectionDAGLowering *SDL;
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SelectionDAGBuilder *SDB;
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MachineBasicBlock *BB;
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AliasAnalysis *AA;
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GCFunctionInfo *GFI;
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@ -16,7 +16,7 @@ add_llvm_library(LLVMSelectionDAG
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ScheduleDAGRRList.cpp
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ScheduleDAGSDNodes.cpp
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SelectionDAG.cpp
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SelectionDAGBuild.cpp
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SelectionDAGBuilder.cpp
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SelectionDAGISel.cpp
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SelectionDAGPrinter.cpp
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TargetLowering.cpp
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@ -54,7 +54,7 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "SelectionDAGBuild.h"
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#include "SelectionDAGBuilder.h"
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#include "FunctionLoweringInfo.h"
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using namespace llvm;
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@ -1,4 +1,4 @@
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//===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
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//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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#include "SelectionDAGBuild.h"
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#include "SelectionDAGBuilder.h"
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#include "FunctionLoweringInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallSet.h"
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@ -501,19 +501,19 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
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}
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void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
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void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
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AA = &aa;
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GFI = gfi;
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TD = DAG.getTarget().getTargetData();
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}
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/// clear - Clear out the curret SelectionDAG and the associated
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/// state and prepare this SelectionDAGLowering object to be used
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/// state and prepare this SelectionDAGBuilder object to be used
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/// for a new block. This doesn't clear out information about
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/// additional blocks that are needed to complete switch lowering
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/// or PHI node updating; that information is cleared out as it is
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/// consumed.
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void SelectionDAGLowering::clear() {
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void SelectionDAGBuilder::clear() {
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NodeMap.clear();
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PendingLoads.clear();
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PendingExports.clear();
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@ -528,7 +528,7 @@ void SelectionDAGLowering::clear() {
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/// a store or any other node that may need to be ordered after any
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/// prior load instructions.
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///
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SDValue SelectionDAGLowering::getRoot() {
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SDValue SelectionDAGBuilder::getRoot() {
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if (PendingLoads.empty())
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return DAG.getRoot();
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@ -551,7 +551,7 @@ SDValue SelectionDAGLowering::getRoot() {
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/// PendingLoad items, flush all the PendingExports items. It is necessary
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/// to do this before emitting a terminator instruction.
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///
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SDValue SelectionDAGLowering::getControlRoot() {
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SDValue SelectionDAGBuilder::getControlRoot() {
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SDValue Root = DAG.getRoot();
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if (PendingExports.empty())
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@ -578,11 +578,11 @@ SDValue SelectionDAGLowering::getControlRoot() {
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return Root;
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}
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void SelectionDAGLowering::visit(Instruction &I) {
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void SelectionDAGBuilder::visit(Instruction &I) {
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visit(I.getOpcode(), I);
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}
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void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
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void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
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// Note: this doesn't use InstVisitor, because it has to work with
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// ConstantExpr's in addition to instructions.
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switch (Opcode) {
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@ -594,7 +594,7 @@ void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
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}
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}
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SDValue SelectionDAGLowering::getValue(const Value *V) {
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SDValue SelectionDAGBuilder::getValue(const Value *V) {
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SDValue &N = NodeMap[V];
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if (N.getNode()) return N;
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@ -759,7 +759,7 @@ static void getReturnInfo(const Type* ReturnType,
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}
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}
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void SelectionDAGLowering::visitRet(ReturnInst &I) {
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void SelectionDAGBuilder::visitRet(ReturnInst &I) {
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SDValue Chain = getControlRoot();
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SmallVector<ISD::OutputArg, 8> Outs;
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FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
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@ -864,7 +864,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
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/// CopyToExportRegsIfNeeded - If the given value has virtual registers
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/// created for it, emit nodes to copy the value into the virtual
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/// registers.
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void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
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void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) {
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if (!V->use_empty()) {
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DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
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if (VMI != FuncInfo.ValueMap.end())
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@ -875,7 +875,7 @@ void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
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/// ExportFromCurrentBlock - If this condition isn't known to be exported from
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/// the current basic block, add it to ValueMap now so that we'll get a
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/// CopyTo/FromReg.
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void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
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void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) {
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// No need to export constants.
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if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
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@ -886,8 +886,8 @@ void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
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CopyValueToVirtualRegister(V, Reg);
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}
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bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
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const BasicBlock *FromBB) {
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bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V,
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const BasicBlock *FromBB) {
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// The operands of the setcc have to be in this block. We don't know
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// how to export them from some other block.
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if (Instruction *VI = dyn_cast<Instruction>(V)) {
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@ -979,10 +979,10 @@ static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
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/// AND operator tree.
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///
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void
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SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB) {
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SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB) {
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const BasicBlock *BB = CurBB->getBasicBlock();
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// If the leaf of the tree is a comparison, merge the condition into
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@ -1018,11 +1018,11 @@ SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
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}
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/// FindMergedConditions - If Cond is an expression like
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void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB,
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unsigned Opc) {
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void SelectionDAGBuilder::FindMergedConditions(Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB,
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unsigned Opc) {
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// If this node is not part of the or/and tree, emit it as a branch.
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Instruction *BOp = dyn_cast<Instruction>(Cond);
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if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
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@ -1077,7 +1077,7 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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/// If we should emit this as a bunch of and/or'd together conditions, return
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/// false.
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bool
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SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
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SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
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if (Cases.size() != 2) return true;
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// If this is two comparisons of the same values or'd or and'd together, they
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@ -1092,7 +1092,7 @@ SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
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return true;
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}
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void SelectionDAGLowering::visitBr(BranchInst &I) {
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void SelectionDAGBuilder::visitBr(BranchInst &I) {
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// Update machine-CFG edges.
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MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
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@ -1176,7 +1176,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
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/// visitSwitchCase - Emits the necessary code to represent a single node in
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/// the binary search tree resulting from lowering a switch instruction.
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void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
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void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
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SDValue Cond;
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SDValue CondLHS = getValue(CB.CmpLHS);
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DebugLoc dl = getCurDebugLoc();
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@ -1254,7 +1254,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
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}
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/// visitJumpTable - Emit JumpTable node in the current MBB
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void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
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void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
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// Emit the code for the jump table
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assert(JT.Reg != -1U && "Should lower JT Header first!");
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EVT PTy = TLI.getPointerTy();
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@ -1268,8 +1268,8 @@ void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
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/// visitJumpTableHeader - This function emits necessary code to produce index
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/// in the JumpTable from switch case.
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void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
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JumpTableHeader &JTH) {
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void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
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JumpTableHeader &JTH) {
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// Subtract the lowest switch case value from the value being switched on and
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// conditional branch to default mbb if the result is greater than the
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// difference between smallest and largest cases.
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@ -1318,7 +1318,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
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/// visitBitTestHeader - This function emits necessary code to produce value
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/// suitable for "bit tests"
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void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
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void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
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// Subtract the minimum value
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SDValue SwitchOp = getValue(B.SValue);
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EVT VT = SwitchOp.getValueType();
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@ -1361,9 +1361,9 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
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}
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/// visitBitTestCase - this function produces one "bit test"
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void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
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unsigned Reg,
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BitTestCase &B) {
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void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
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unsigned Reg,
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BitTestCase &B) {
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// Make desired shift
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SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
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TLI.getPointerTy());
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@ -1402,7 +1402,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
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DAG.getBasicBlock(NextMBB)));
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}
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void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
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void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
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// Retrieve successors.
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MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
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MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
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@ -1427,15 +1427,15 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
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DAG.getBasicBlock(Return)));
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}
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void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
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void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
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}
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/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
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/// small case ranges).
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bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default) {
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bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default) {
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Case& BackCase = *(CR.Range.second-1);
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// Size is the number of Cases represented by this range.
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@ -1529,10 +1529,10 @@ static APInt ComputeRange(const APInt &First, const APInt &Last) {
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}
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/// handleJTSwitchCase - Emit jumptable for current switch case range
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bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default) {
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bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default) {
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Case& FrontCase = *CR.Range.first;
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Case& BackCase = *(CR.Range.second-1);
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@ -1623,10 +1623,10 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
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/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
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/// 2 subtrees.
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bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default) {
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bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default) {
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// Get the MachineFunction which holds the current MBB. This is used when
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// inserting any additional MBBs necessary to represent the switch.
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MachineFunction *CurMF = FuncInfo.MF;
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@ -1751,10 +1751,10 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
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/// handleBitTestsSwitchCase - if current case range has few destination and
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/// range span less, than machine word bitwidth, encode case range into series
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/// of masks and emit bit tests with these masks.
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bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default){
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bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default){
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EVT PTy = TLI.getPointerTy();
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unsigned IntPtrBits = PTy.getSizeInBits();
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@ -1882,8 +1882,8 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
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/// Clusterify - Transform simple list of Cases into list of CaseRange's
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size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
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const SwitchInst& SI) {
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size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
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const SwitchInst& SI) {
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size_t numCmps = 0;
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// Start with "simple" cases
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@ -1924,7 +1924,7 @@ size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
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return numCmps;
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}
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void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
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void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
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// Figure out which block is immediately after the current one.
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MachineBasicBlock *NextBlock = 0;
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@ -1987,7 +1987,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
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}
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}
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void SelectionDAGLowering::visitIndirectBr(IndirectBrInst &I) {
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void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
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// Update machine-CFG edges.
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for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
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CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);
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@ -1998,7 +1998,7 @@ void SelectionDAGLowering::visitIndirectBr(IndirectBrInst &I) {
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}
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void SelectionDAGLowering::visitFSub(User &I) {
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void SelectionDAGBuilder::visitFSub(User &I) {
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// -0.0 - X --> fneg
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const Type *Ty = I.getType();
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if (isa<VectorType>(Ty)) {
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@ -2027,7 +2027,7 @@ void SelectionDAGLowering::visitFSub(User &I) {
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visitBinary(I, ISD::FSUB);
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}
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void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
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void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
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SDValue Op1 = getValue(I.getOperand(0));
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SDValue Op2 = getValue(I.getOperand(1));
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@ -2035,7 +2035,7 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
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Op1.getValueType(), Op1, Op2));
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}
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void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
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void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
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SDValue Op1 = getValue(I.getOperand(0));
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SDValue Op2 = getValue(I.getOperand(1));
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if (!isa<VectorType>(I.getType()) &&
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@ -2069,7 +2069,7 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
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Op1.getValueType(), Op1, Op2));
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}
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void SelectionDAGLowering::visitICmp(User &I) {
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void SelectionDAGBuilder::visitICmp(User &I) {
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ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
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if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
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predicate = IC->getPredicate();
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@ -2083,7 +2083,7 @@ void SelectionDAGLowering::visitICmp(User &I) {
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setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
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}
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void SelectionDAGLowering::visitFCmp(User &I) {
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void SelectionDAGBuilder::visitFCmp(User &I) {
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FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
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if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
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predicate = FC->getPredicate();
|
||||
@ -2096,7 +2096,7 @@ void SelectionDAGLowering::visitFCmp(User &I) {
|
||||
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitSelect(User &I) {
|
||||
void SelectionDAGBuilder::visitSelect(User &I) {
|
||||
SmallVector<EVT, 4> ValueVTs;
|
||||
ComputeValueVTs(TLI, I.getType(), ValueVTs);
|
||||
unsigned NumValues = ValueVTs.size();
|
||||
@ -2119,14 +2119,14 @@ void SelectionDAGLowering::visitSelect(User &I) {
|
||||
}
|
||||
|
||||
|
||||
void SelectionDAGLowering::visitTrunc(User &I) {
|
||||
void SelectionDAGBuilder::visitTrunc(User &I) {
|
||||
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitZExt(User &I) {
|
||||
void SelectionDAGBuilder::visitZExt(User &I) {
|
||||
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
|
||||
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
@ -2134,7 +2134,7 @@ void SelectionDAGLowering::visitZExt(User &I) {
|
||||
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitSExt(User &I) {
|
||||
void SelectionDAGBuilder::visitSExt(User &I) {
|
||||
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
|
||||
// SExt also can't be a cast to bool for same reason. So, nothing much to do
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
@ -2142,7 +2142,7 @@ void SelectionDAGLowering::visitSExt(User &I) {
|
||||
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitFPTrunc(User &I) {
|
||||
void SelectionDAGBuilder::visitFPTrunc(User &I) {
|
||||
// FPTrunc is never a no-op cast, no need to check
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
@ -2150,42 +2150,42 @@ void SelectionDAGLowering::visitFPTrunc(User &I) {
|
||||
DestVT, N, DAG.getIntPtrConstant(0)));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitFPExt(User &I){
|
||||
void SelectionDAGBuilder::visitFPExt(User &I){
|
||||
// FPTrunc is never a no-op cast, no need to check
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitFPToUI(User &I) {
|
||||
void SelectionDAGBuilder::visitFPToUI(User &I) {
|
||||
// FPToUI is never a no-op cast, no need to check
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitFPToSI(User &I) {
|
||||
void SelectionDAGBuilder::visitFPToSI(User &I) {
|
||||
// FPToSI is never a no-op cast, no need to check
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitUIToFP(User &I) {
|
||||
void SelectionDAGBuilder::visitUIToFP(User &I) {
|
||||
// UIToFP is never a no-op cast, no need to check
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitSIToFP(User &I){
|
||||
void SelectionDAGBuilder::visitSIToFP(User &I){
|
||||
// SIToFP is never a no-op cast, no need to check
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitPtrToInt(User &I) {
|
||||
void SelectionDAGBuilder::visitPtrToInt(User &I) {
|
||||
// What to do depends on the size of the integer and the size of the pointer.
|
||||
// We can either truncate, zero extend, or no-op, accordingly.
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
@ -2195,7 +2195,7 @@ void SelectionDAGLowering::visitPtrToInt(User &I) {
|
||||
setValue(&I, Result);
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitIntToPtr(User &I) {
|
||||
void SelectionDAGBuilder::visitIntToPtr(User &I) {
|
||||
// What to do depends on the size of the integer and the size of the pointer.
|
||||
// We can either truncate, zero extend, or no-op, accordingly.
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
@ -2204,7 +2204,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) {
|
||||
setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitBitCast(User &I) {
|
||||
void SelectionDAGBuilder::visitBitCast(User &I) {
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
EVT DestVT = TLI.getValueType(I.getType());
|
||||
|
||||
@ -2217,7 +2217,7 @@ void SelectionDAGLowering::visitBitCast(User &I) {
|
||||
setValue(&I, N); // noop cast.
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitInsertElement(User &I) {
|
||||
void SelectionDAGBuilder::visitInsertElement(User &I) {
|
||||
SDValue InVec = getValue(I.getOperand(0));
|
||||
SDValue InVal = getValue(I.getOperand(1));
|
||||
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
|
||||
@ -2229,7 +2229,7 @@ void SelectionDAGLowering::visitInsertElement(User &I) {
|
||||
InVec, InVal, InIdx));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitExtractElement(User &I) {
|
||||
void SelectionDAGBuilder::visitExtractElement(User &I) {
|
||||
SDValue InVec = getValue(I.getOperand(0));
|
||||
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
|
||||
TLI.getPointerTy(),
|
||||
@ -2249,7 +2249,7 @@ static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
|
||||
return true;
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
void SelectionDAGBuilder::visitShuffleVector(User &I) {
|
||||
SmallVector<int, 8> Mask;
|
||||
SDValue Src1 = getValue(I.getOperand(0));
|
||||
SDValue Src2 = getValue(I.getOperand(1));
|
||||
@ -2423,7 +2423,7 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
VT, &Ops[0], Ops.size()));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
|
||||
void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) {
|
||||
const Value *Op0 = I.getOperand(0);
|
||||
const Value *Op1 = I.getOperand(1);
|
||||
const Type *AggTy = I.getType();
|
||||
@ -2464,7 +2464,7 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
|
||||
&Values[0], NumAggValues));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
|
||||
void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) {
|
||||
const Value *Op0 = I.getOperand(0);
|
||||
const Type *AggTy = Op0->getType();
|
||||
const Type *ValTy = I.getType();
|
||||
@ -2493,7 +2493,7 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
|
||||
}
|
||||
|
||||
|
||||
void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
||||
void SelectionDAGBuilder::visitGetElementPtr(User &I) {
|
||||
SDValue N = getValue(I.getOperand(0));
|
||||
const Type *Ty = I.getOperand(0)->getType();
|
||||
|
||||
@ -2562,7 +2562,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
||||
setValue(&I, N);
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
||||
void SelectionDAGBuilder::visitAlloca(AllocaInst &I) {
|
||||
// If this is a fixed sized alloca in the entry block of the function,
|
||||
// allocate it statically on the stack.
|
||||
if (FuncInfo.StaticAllocaMap.count(&I))
|
||||
@ -2615,7 +2615,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
||||
FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitLoad(LoadInst &I) {
|
||||
void SelectionDAGBuilder::visitLoad(LoadInst &I) {
|
||||
const Value *SV = I.getOperand(0);
|
||||
SDValue Ptr = getValue(SV);
|
||||
|
||||
@ -2673,7 +2673,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
|
||||
}
|
||||
|
||||
|
||||
void SelectionDAGLowering::visitStore(StoreInst &I) {
|
||||
void SelectionDAGBuilder::visitStore(StoreInst &I) {
|
||||
Value *SrcV = I.getOperand(0);
|
||||
Value *PtrV = I.getOperand(1);
|
||||
|
||||
@ -2709,8 +2709,8 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
|
||||
|
||||
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
|
||||
/// node.
|
||||
void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
|
||||
unsigned Intrinsic) {
|
||||
void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
|
||||
unsigned Intrinsic) {
|
||||
bool HasChain = !I.doesNotAccessMemory();
|
||||
bool OnlyLoad = HasChain && I.onlyReadsMemory();
|
||||
|
||||
@ -2832,7 +2832,7 @@ getF32Constant(SelectionDAG &DAG, unsigned Flt) {
|
||||
/// visitIntrinsicCall: I is a call instruction
|
||||
/// Op is the associated NodeType for I
|
||||
const char *
|
||||
SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
|
||||
SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
|
||||
SDValue Root = getRoot();
|
||||
SDValue L =
|
||||
DAG.getAtomic(Op, getCurDebugLoc(),
|
||||
@ -2848,7 +2848,7 @@ SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
|
||||
|
||||
// implVisitAluOverflow - Lower arithmetic overflow instrinsics.
|
||||
const char *
|
||||
SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
|
||||
SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
|
||||
SDValue Op1 = getValue(I.getOperand(1));
|
||||
SDValue Op2 = getValue(I.getOperand(2));
|
||||
|
||||
@ -2862,7 +2862,7 @@ SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
|
||||
/// visitExp - Lower an exp intrinsic. Handles the special sequences for
|
||||
/// limited-precision mode.
|
||||
void
|
||||
SelectionDAGLowering::visitExp(CallInst &I) {
|
||||
SelectionDAGBuilder::visitExp(CallInst &I) {
|
||||
SDValue result;
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
|
||||
@ -2988,7 +2988,7 @@ SelectionDAGLowering::visitExp(CallInst &I) {
|
||||
/// visitLog - Lower a log intrinsic. Handles the special sequences for
|
||||
/// limited-precision mode.
|
||||
void
|
||||
SelectionDAGLowering::visitLog(CallInst &I) {
|
||||
SelectionDAGBuilder::visitLog(CallInst &I) {
|
||||
SDValue result;
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
|
||||
@ -3098,7 +3098,7 @@ SelectionDAGLowering::visitLog(CallInst &I) {
|
||||
/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
|
||||
/// limited-precision mode.
|
||||
void
|
||||
SelectionDAGLowering::visitLog2(CallInst &I) {
|
||||
SelectionDAGBuilder::visitLog2(CallInst &I) {
|
||||
SDValue result;
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
|
||||
@ -3207,7 +3207,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
|
||||
/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
|
||||
/// limited-precision mode.
|
||||
void
|
||||
SelectionDAGLowering::visitLog10(CallInst &I) {
|
||||
SelectionDAGBuilder::visitLog10(CallInst &I) {
|
||||
SDValue result;
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
|
||||
@ -3309,7 +3309,7 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
|
||||
/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
|
||||
/// limited-precision mode.
|
||||
void
|
||||
SelectionDAGLowering::visitExp2(CallInst &I) {
|
||||
SelectionDAGBuilder::visitExp2(CallInst &I) {
|
||||
SDValue result;
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
|
||||
@ -3423,7 +3423,7 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
|
||||
/// visitPow - Lower a pow intrinsic. Handles the special sequences for
|
||||
/// limited-precision mode with x == 10.0f.
|
||||
void
|
||||
SelectionDAGLowering::visitPow(CallInst &I) {
|
||||
SelectionDAGBuilder::visitPow(CallInst &I) {
|
||||
SDValue result;
|
||||
Value *Val = I.getOperand(1);
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
@ -3558,7 +3558,7 @@ SelectionDAGLowering::visitPow(CallInst &I) {
|
||||
/// we want to emit this as a call to a named external function, return the name
|
||||
/// otherwise lower it and return null.
|
||||
const char *
|
||||
SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
DebugLoc dl = getCurDebugLoc();
|
||||
switch (Intrinsic) {
|
||||
default:
|
||||
@ -4123,9 +4123,9 @@ isInTailCallPosition(const Instruction *I, Attributes CalleeRetAttr,
|
||||
return true;
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
|
||||
bool isTailCall,
|
||||
MachineBasicBlock *LandingPad) {
|
||||
void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
|
||||
bool isTailCall,
|
||||
MachineBasicBlock *LandingPad) {
|
||||
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
|
||||
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
||||
const Type *RetTy = FTy->getReturnType();
|
||||
@ -4272,7 +4272,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
|
||||
}
|
||||
|
||||
|
||||
void SelectionDAGLowering::visitCall(CallInst &I) {
|
||||
void SelectionDAGBuilder::visitCall(CallInst &I) {
|
||||
const char *RenameFn = 0;
|
||||
if (Function *F = I.getCalledFunction()) {
|
||||
if (F->isDeclaration()) {
|
||||
@ -4667,7 +4667,7 @@ private:
|
||||
/// OpInfo describes the operand.
|
||||
/// Input and OutputRegs are the set of already allocated physical registers.
|
||||
///
|
||||
void SelectionDAGLowering::
|
||||
void SelectionDAGBuilder::
|
||||
GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
|
||||
std::set<unsigned> &OutputRegs,
|
||||
std::set<unsigned> &InputRegs) {
|
||||
@ -4861,7 +4861,7 @@ hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
|
||||
|
||||
/// visitInlineAsm - Handle a call to an InlineAsm object.
|
||||
///
|
||||
void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
|
||||
void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
|
||||
InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
|
||||
|
||||
/// ConstraintOperands - Information about all of the constraints.
|
||||
@ -5283,14 +5283,14 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
|
||||
DAG.setRoot(Chain);
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitVAStart(CallInst &I) {
|
||||
void SelectionDAGBuilder::visitVAStart(CallInst &I) {
|
||||
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
|
||||
MVT::Other, getRoot(),
|
||||
getValue(I.getOperand(1)),
|
||||
DAG.getSrcValue(I.getOperand(1))));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
|
||||
void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
|
||||
SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
|
||||
getRoot(), getValue(I.getOperand(0)),
|
||||
DAG.getSrcValue(I.getOperand(0)));
|
||||
@ -5298,14 +5298,14 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
|
||||
DAG.setRoot(V.getValue(1));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
|
||||
void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
|
||||
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
|
||||
MVT::Other, getRoot(),
|
||||
getValue(I.getOperand(1)),
|
||||
DAG.getSrcValue(I.getOperand(1))));
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitVACopy(CallInst &I) {
|
||||
void SelectionDAGBuilder::visitVACopy(CallInst &I) {
|
||||
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
|
||||
MVT::Other, getRoot(),
|
||||
getValue(I.getOperand(1)),
|
||||
@ -5498,7 +5498,7 @@ SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
|
||||
}
|
||||
|
||||
|
||||
void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
|
||||
void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
|
||||
SDValue Op = getValue(V);
|
||||
assert((Op.getOpcode() != ISD::CopyFromReg ||
|
||||
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
|
||||
@ -5516,9 +5516,9 @@ void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
|
||||
void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
|
||||
// If this is the entry block, emit arguments.
|
||||
Function &F = *LLVMBB->getParent();
|
||||
SelectionDAG &DAG = SDL->DAG;
|
||||
SelectionDAG &DAG = SDB->DAG;
|
||||
SDValue OldRoot = DAG.getRoot();
|
||||
DebugLoc dl = SDL->getCurDebugLoc();
|
||||
DebugLoc dl = SDB->getCurDebugLoc();
|
||||
const TargetData *TD = TLI.getTargetData();
|
||||
SmallVector<ISD::InputArg, 16> Ins;
|
||||
|
||||
@ -5634,11 +5634,11 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
|
||||
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT,
|
||||
VT, AssertOp);
|
||||
|
||||
MachineFunction& MF = SDL->DAG.getMachineFunction();
|
||||
MachineFunction& MF = SDB->DAG.getMachineFunction();
|
||||
MachineRegisterInfo& RegInfo = MF.getRegInfo();
|
||||
unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
|
||||
FLI.DemoteRegister = SRetReg;
|
||||
NewRoot = SDL->DAG.getCopyToReg(NewRoot, SDL->getCurDebugLoc(), SRetReg, ArgValue);
|
||||
NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), SRetReg, ArgValue);
|
||||
DAG.setRoot(NewRoot);
|
||||
|
||||
// i indexes lowered arguments. Bump it past the hidden sret argument.
|
||||
@ -5669,18 +5669,18 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
|
||||
i += NumParts;
|
||||
}
|
||||
if (!I->use_empty()) {
|
||||
SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
|
||||
SDL->getCurDebugLoc()));
|
||||
SDB->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
|
||||
SDB->getCurDebugLoc()));
|
||||
// If this argument is live outside of the entry block, insert a copy from
|
||||
// whereever we got it to the vreg that other BB's will reference it as.
|
||||
SDL->CopyToExportRegsIfNeeded(I);
|
||||
SDB->CopyToExportRegsIfNeeded(I);
|
||||
}
|
||||
}
|
||||
assert(i == InVals.size() && "Argument register count mismatch!");
|
||||
|
||||
// Finally, if the target has anything special to do, allow it to do so.
|
||||
// FIXME: this should insert code into the DAG!
|
||||
EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
|
||||
EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction());
|
||||
}
|
||||
|
||||
/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
|
||||
@ -5722,10 +5722,10 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
|
||||
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
|
||||
|
||||
if (Constant *C = dyn_cast<Constant>(PHIOp)) {
|
||||
unsigned &RegOut = SDL->ConstantsOut[C];
|
||||
unsigned &RegOut = SDB->ConstantsOut[C];
|
||||
if (RegOut == 0) {
|
||||
RegOut = FuncInfo->CreateRegForValue(C);
|
||||
SDL->CopyValueToVirtualRegister(C, RegOut);
|
||||
SDB->CopyValueToVirtualRegister(C, RegOut);
|
||||
}
|
||||
Reg = RegOut;
|
||||
} else {
|
||||
@ -5735,7 +5735,7 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
|
||||
FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
|
||||
"Didn't codegen value into a register!??");
|
||||
Reg = FuncInfo->CreateRegForValue(PHIOp);
|
||||
SDL->CopyValueToVirtualRegister(PHIOp, Reg);
|
||||
SDB->CopyValueToVirtualRegister(PHIOp, Reg);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5747,12 +5747,12 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
|
||||
EVT VT = ValueVTs[vti];
|
||||
unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
|
||||
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
|
||||
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
|
||||
SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
|
||||
Reg += NumRegisters;
|
||||
}
|
||||
}
|
||||
}
|
||||
SDL->ConstantsOut.clear();
|
||||
SDB->ConstantsOut.clear();
|
||||
}
|
||||
|
||||
/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
|
||||
@ -5765,7 +5765,7 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
|
||||
TerminatorInst *TI = LLVMBB->getTerminator();
|
||||
|
||||
SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
|
||||
unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
|
||||
unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
|
||||
|
||||
// Check successor nodes' PHI nodes that expect a constant to be available
|
||||
// from this block.
|
||||
@ -5801,7 +5801,7 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
|
||||
if (VT == MVT::i1)
|
||||
VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
|
||||
else {
|
||||
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
|
||||
SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
@ -5810,10 +5810,10 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
|
||||
|
||||
unsigned Reg = F->getRegForValue(PHIOp);
|
||||
if (Reg == 0) {
|
||||
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
|
||||
SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
|
||||
return false;
|
||||
}
|
||||
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
|
||||
SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- SelectionDAGBuild.h - Selection-DAG building ----------------------===//
|
||||
//===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -11,8 +11,8 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SELECTIONDAGBUILD_H
|
||||
#define SELECTIONDAGBUILD_H
|
||||
#ifndef SELECTIONDAGBUILDER_H
|
||||
#define SELECTIONDAGBUILDER_H
|
||||
|
||||
#include "llvm/Constants.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
@ -79,11 +79,11 @@ class VAArgInst;
|
||||
class ZExtInst;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// SelectionDAGLowering - This is the common target-independent lowering
|
||||
/// SelectionDAGBuilder - This is the common target-independent lowering
|
||||
/// implementation that is parameterized by a TargetLowering object.
|
||||
/// Also, targets can overload any lowering method.
|
||||
///
|
||||
class SelectionDAGLowering {
|
||||
class SelectionDAGBuilder {
|
||||
MachineBasicBlock *CurMBB;
|
||||
|
||||
/// CurDebugLoc - current file + line number. Changes as we build the DAG.
|
||||
@ -173,9 +173,9 @@ class SelectionDAGLowering {
|
||||
|
||||
size_t Clusterify(CaseVector& Cases, const SwitchInst &SI);
|
||||
|
||||
/// CaseBlock - This structure is used to communicate between SDLowering and
|
||||
/// SDISel for the code generation of additional basic blocks needed by multi-
|
||||
/// case switch statements.
|
||||
/// CaseBlock - This structure is used to communicate between
|
||||
/// SelectionDAGBuilder and SDISel for the code generation of additional basic
|
||||
/// blocks needed by multi-case switch statements.
|
||||
struct CaseBlock {
|
||||
CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
|
||||
MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
|
||||
@ -297,9 +297,9 @@ public:
|
||||
|
||||
LLVMContext *Context;
|
||||
|
||||
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
|
||||
FunctionLoweringInfo &funcinfo,
|
||||
CodeGenOpt::Level ol)
|
||||
SelectionDAGBuilder(SelectionDAG &dag, TargetLowering &tli,
|
||||
FunctionLoweringInfo &funcinfo,
|
||||
CodeGenOpt::Level ol)
|
||||
: CurDebugLoc(DebugLoc::getUnknownLoc()),
|
||||
TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
|
||||
HasTailCall(false),
|
||||
@ -309,7 +309,7 @@ public:
|
||||
void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
|
||||
|
||||
/// clear - Clear out the curret SelectionDAG and the associated
|
||||
/// state and prepare this SelectionDAGLowering object to be used
|
||||
/// state and prepare this SelectionDAGBuilder object to be used
|
||||
/// for a new block. This doesn't clear out information about
|
||||
/// additional blocks that are needed to complete switch lowering
|
||||
/// or PHI node updating; that information is cleared out as it is
|
||||
@ -13,7 +13,7 @@
|
||||
|
||||
#define DEBUG_TYPE "isel"
|
||||
#include "ScheduleDAGSDNodes.h"
|
||||
#include "SelectionDAGBuild.h"
|
||||
#include "SelectionDAGBuilder.h"
|
||||
#include "FunctionLoweringInfo.h"
|
||||
#include "llvm/CodeGen/SelectionDAGISel.h"
|
||||
#include "llvm/Analysis/AliasAnalysis.h"
|
||||
@ -280,14 +280,14 @@ SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
|
||||
MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
|
||||
FuncInfo(new FunctionLoweringInfo(TLI)),
|
||||
CurDAG(new SelectionDAG(TLI, *FuncInfo)),
|
||||
SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
|
||||
SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
|
||||
GFI(),
|
||||
OptLevel(OL),
|
||||
DAGSize(0)
|
||||
{}
|
||||
|
||||
SelectionDAGISel::~SelectionDAGISel() {
|
||||
delete SDL;
|
||||
delete SDB;
|
||||
delete CurDAG;
|
||||
delete FuncInfo;
|
||||
}
|
||||
@ -333,7 +333,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
|
||||
DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
|
||||
CurDAG->init(*MF, MMI, DW);
|
||||
FuncInfo->set(Fn, *MF, EnableFastISel);
|
||||
SDL->init(GFI, *AA);
|
||||
SDB->init(GFI, *AA);
|
||||
|
||||
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
|
||||
if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
|
||||
@ -379,13 +379,13 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
|
||||
BasicBlock::iterator Begin,
|
||||
BasicBlock::iterator End,
|
||||
bool &HadTailCall) {
|
||||
SDL->setCurrentBasicBlock(BB);
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata();
|
||||
unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
|
||||
|
||||
// Lower all of the non-terminator instructions. If a call is emitted
|
||||
// as a tail call, cease emitting nodes for this block.
|
||||
for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) {
|
||||
for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
|
||||
if (MDDbgKind) {
|
||||
// Update DebugLoc if debug information is attached with this
|
||||
// instruction.
|
||||
@ -393,38 +393,38 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
|
||||
if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) {
|
||||
DILocation DILoc(Dbg);
|
||||
DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
|
||||
SDL->setCurDebugLoc(Loc);
|
||||
SDB->setCurDebugLoc(Loc);
|
||||
if (MF->getDefaultDebugLoc().isUnknown())
|
||||
MF->setDefaultDebugLoc(Loc);
|
||||
}
|
||||
}
|
||||
if (!isa<TerminatorInst>(I))
|
||||
SDL->visit(*I);
|
||||
SDB->visit(*I);
|
||||
}
|
||||
|
||||
if (!SDL->HasTailCall) {
|
||||
if (!SDB->HasTailCall) {
|
||||
// Ensure that all instructions which are used outside of their defining
|
||||
// blocks are available as virtual registers. Invoke is handled elsewhere.
|
||||
for (BasicBlock::iterator I = Begin; I != End; ++I)
|
||||
if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
|
||||
SDL->CopyToExportRegsIfNeeded(I);
|
||||
SDB->CopyToExportRegsIfNeeded(I);
|
||||
|
||||
// Handle PHI nodes in successor blocks.
|
||||
if (End == LLVMBB->end()) {
|
||||
HandlePHINodesInSuccessorBlocks(LLVMBB);
|
||||
|
||||
// Lower the terminator after the copies are emitted.
|
||||
SDL->visit(*LLVMBB->getTerminator());
|
||||
SDB->visit(*LLVMBB->getTerminator());
|
||||
}
|
||||
}
|
||||
|
||||
// Make sure the root of the DAG is up-to-date.
|
||||
CurDAG->setRoot(SDL->getControlRoot());
|
||||
CurDAG->setRoot(SDB->getControlRoot());
|
||||
|
||||
// Final step, emit the lowered DAG as machine code.
|
||||
CodeGenAndEmitDAG();
|
||||
HadTailCall = SDL->HasTailCall;
|
||||
SDL->clear();
|
||||
HadTailCall = SDB->HasTailCall;
|
||||
SDB->clear();
|
||||
}
|
||||
|
||||
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
|
||||
@ -632,9 +632,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
|
||||
// inserted into.
|
||||
if (TimePassesIsEnabled) {
|
||||
NamedRegionTimer T("Instruction Creation", GroupName);
|
||||
BB = Scheduler->EmitSchedule(&SDL->EdgeMapping);
|
||||
BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
|
||||
} else {
|
||||
BB = Scheduler->EmitSchedule(&SDL->EdgeMapping);
|
||||
BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
|
||||
}
|
||||
|
||||
// Free the scheduler state.
|
||||
@ -704,7 +704,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
|
||||
unsigned LabelID = MMI->addLandingPad(BB);
|
||||
|
||||
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
|
||||
BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID);
|
||||
BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
|
||||
|
||||
// Mark exception register as live in.
|
||||
unsigned Reg = TLI.getExceptionAddressRegister();
|
||||
@ -744,9 +744,9 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
|
||||
// Emit code for any incoming arguments. This must happen before
|
||||
// beginning FastISel on the entry block.
|
||||
if (LLVMBB == &Fn.getEntryBlock()) {
|
||||
CurDAG->setRoot(SDL->getControlRoot());
|
||||
CurDAG->setRoot(SDB->getControlRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDL->clear();
|
||||
SDB->clear();
|
||||
}
|
||||
FastIS->startNewBlock(BB);
|
||||
// Do FastISel on as many instructions as possible.
|
||||
@ -799,7 +799,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
|
||||
R = FuncInfo->CreateRegForValue(BI);
|
||||
}
|
||||
|
||||
SDL->setCurDebugLoc(FastIS->getCurDebugLoc());
|
||||
SDB->setCurDebugLoc(FastIS->getCurDebugLoc());
|
||||
|
||||
bool HadTailCall = false;
|
||||
SelectBasicBlock(LLVMBB, BI, next(BI), HadTailCall);
|
||||
@ -838,7 +838,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
|
||||
if (BI != End) {
|
||||
// If FastISel is run and it has known DebugLoc then use it.
|
||||
if (FastIS && !FastIS->getCurDebugLoc().isUnknown())
|
||||
SDL->setCurDebugLoc(FastIS->getCurDebugLoc());
|
||||
SDB->setCurDebugLoc(FastIS->getCurDebugLoc());
|
||||
bool HadTailCall;
|
||||
SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
|
||||
}
|
||||
@ -856,150 +856,150 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
DEBUG(BB->dump());
|
||||
|
||||
DEBUG(errs() << "Total amount of phi nodes to update: "
|
||||
<< SDL->PHINodesToUpdate.size() << "\n");
|
||||
DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
|
||||
<< SDB->PHINodesToUpdate.size() << "\n");
|
||||
DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
|
||||
errs() << "Node " << i << " : ("
|
||||
<< SDL->PHINodesToUpdate[i].first
|
||||
<< ", " << SDL->PHINodesToUpdate[i].second << ")\n");
|
||||
<< SDB->PHINodesToUpdate[i].first
|
||||
<< ", " << SDB->PHINodesToUpdate[i].second << ")\n");
|
||||
|
||||
// Next, now that we know what the last MBB the LLVM BB expanded is, update
|
||||
// PHI nodes in successors.
|
||||
if (SDL->SwitchCases.empty() &&
|
||||
SDL->JTCases.empty() &&
|
||||
SDL->BitTestCases.empty()) {
|
||||
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
|
||||
MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
|
||||
if (SDB->SwitchCases.empty() &&
|
||||
SDB->JTCases.empty() &&
|
||||
SDB->BitTestCases.empty()) {
|
||||
for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
|
||||
MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
|
||||
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
||||
"This is not a machine PHI node that we are updating!");
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
|
||||
false));
|
||||
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
||||
}
|
||||
SDL->PHINodesToUpdate.clear();
|
||||
SDB->PHINodesToUpdate.clear();
|
||||
return;
|
||||
}
|
||||
|
||||
for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
|
||||
for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
|
||||
// Lower header first, if it wasn't already lowered
|
||||
if (!SDL->BitTestCases[i].Emitted) {
|
||||
if (!SDB->BitTestCases[i].Emitted) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDL->BitTestCases[i].Parent;
|
||||
SDL->setCurrentBasicBlock(BB);
|
||||
BB = SDB->BitTestCases[i].Parent;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
SDL->visitBitTestHeader(SDL->BitTestCases[i]);
|
||||
CurDAG->setRoot(SDL->getRoot());
|
||||
SDB->visitBitTestHeader(SDB->BitTestCases[i]);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDL->clear();
|
||||
SDB->clear();
|
||||
}
|
||||
|
||||
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
|
||||
for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDL->BitTestCases[i].Cases[j].ThisBB;
|
||||
SDL->setCurrentBasicBlock(BB);
|
||||
BB = SDB->BitTestCases[i].Cases[j].ThisBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
if (j+1 != ej)
|
||||
SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
|
||||
SDL->BitTestCases[i].Reg,
|
||||
SDL->BitTestCases[i].Cases[j]);
|
||||
SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
|
||||
SDB->BitTestCases[i].Reg,
|
||||
SDB->BitTestCases[i].Cases[j]);
|
||||
else
|
||||
SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
|
||||
SDL->BitTestCases[i].Reg,
|
||||
SDL->BitTestCases[i].Cases[j]);
|
||||
SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
|
||||
SDB->BitTestCases[i].Reg,
|
||||
SDB->BitTestCases[i].Cases[j]);
|
||||
|
||||
|
||||
CurDAG->setRoot(SDL->getRoot());
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDL->clear();
|
||||
SDB->clear();
|
||||
}
|
||||
|
||||
// Update PHI Nodes
|
||||
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
|
||||
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
|
||||
for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
|
||||
MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
|
||||
MachineBasicBlock *PHIBB = PHI->getParent();
|
||||
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
||||
"This is not a machine PHI node that we are updating!");
|
||||
// This is "default" BB. We have two jumps to it. From "header" BB and
|
||||
// from last "case" BB.
|
||||
if (PHIBB == SDL->BitTestCases[i].Default) {
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
||||
if (PHIBB == SDB->BitTestCases[i].Default) {
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
|
||||
false));
|
||||
PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
||||
PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
|
||||
false));
|
||||
PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
|
||||
PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
|
||||
back().ThisBB));
|
||||
}
|
||||
// One of "cases" BB.
|
||||
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
|
||||
for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
|
||||
j != ej; ++j) {
|
||||
MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
|
||||
MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
|
||||
if (cBB->succ_end() !=
|
||||
std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
|
||||
false));
|
||||
PHI->addOperand(MachineOperand::CreateMBB(cBB));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
SDL->BitTestCases.clear();
|
||||
SDB->BitTestCases.clear();
|
||||
|
||||
// If the JumpTable record is filled in, then we need to emit a jump table.
|
||||
// Updating the PHI nodes is tricky in this case, since we need to determine
|
||||
// whether the PHI is a successor of the range check MBB or the jump table MBB
|
||||
for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
|
||||
for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
|
||||
// Lower header first, if it wasn't already lowered
|
||||
if (!SDL->JTCases[i].first.Emitted) {
|
||||
if (!SDB->JTCases[i].first.Emitted) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDL->JTCases[i].first.HeaderBB;
|
||||
SDL->setCurrentBasicBlock(BB);
|
||||
BB = SDB->JTCases[i].first.HeaderBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
|
||||
CurDAG->setRoot(SDL->getRoot());
|
||||
SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDL->clear();
|
||||
SDB->clear();
|
||||
}
|
||||
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDL->JTCases[i].second.MBB;
|
||||
SDL->setCurrentBasicBlock(BB);
|
||||
BB = SDB->JTCases[i].second.MBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
SDL->visitJumpTable(SDL->JTCases[i].second);
|
||||
CurDAG->setRoot(SDL->getRoot());
|
||||
SDB->visitJumpTable(SDB->JTCases[i].second);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDL->clear();
|
||||
SDB->clear();
|
||||
|
||||
// Update PHI Nodes
|
||||
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
|
||||
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
|
||||
for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
|
||||
MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
|
||||
MachineBasicBlock *PHIBB = PHI->getParent();
|
||||
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
||||
"This is not a machine PHI node that we are updating!");
|
||||
// "default" BB. We can go there only from header BB.
|
||||
if (PHIBB == SDL->JTCases[i].second.Default) {
|
||||
if (PHIBB == SDB->JTCases[i].second.Default) {
|
||||
PHI->addOperand
|
||||
(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false));
|
||||
(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
|
||||
PHI->addOperand
|
||||
(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
|
||||
(MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
|
||||
}
|
||||
// JT BB. Just iterate over successors here
|
||||
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
|
||||
PHI->addOperand
|
||||
(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false));
|
||||
(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
|
||||
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
||||
}
|
||||
}
|
||||
}
|
||||
SDL->JTCases.clear();
|
||||
SDB->JTCases.clear();
|
||||
|
||||
// If the switch block involved a branch to one of the actual successors, we
|
||||
// need to update PHI nodes in that block.
|
||||
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
|
||||
MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
|
||||
for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
|
||||
MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
|
||||
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
||||
"This is not a machine PHI node that we are updating!");
|
||||
if (BB->isSuccessor(PHI->getParent())) {
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
|
||||
PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
|
||||
false));
|
||||
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
||||
}
|
||||
@ -1007,36 +1007,36 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
|
||||
// If we generated any switch lowering information, build and codegen any
|
||||
// additional DAGs necessary.
|
||||
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
|
||||
for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
MachineBasicBlock *ThisBB = BB = SDL->SwitchCases[i].ThisBB;
|
||||
SDL->setCurrentBasicBlock(BB);
|
||||
MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
|
||||
// Emit the code
|
||||
SDL->visitSwitchCase(SDL->SwitchCases[i]);
|
||||
CurDAG->setRoot(SDL->getRoot());
|
||||
SDB->visitSwitchCase(SDB->SwitchCases[i]);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
|
||||
// Handle any PHI nodes in successors of this chunk, as if we were coming
|
||||
// from the original BB before switch expansion. Note that PHI nodes can
|
||||
// occur multiple times in PHINodesToUpdate. We have to be very careful to
|
||||
// handle them the right number of times.
|
||||
while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
|
||||
while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
|
||||
// If new BB's are created during scheduling, the edges may have been
|
||||
// updated. That is, the edge from ThisBB to BB may have been split and
|
||||
// BB's predecessor is now another block.
|
||||
DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
|
||||
SDL->EdgeMapping.find(BB);
|
||||
if (EI != SDL->EdgeMapping.end())
|
||||
SDB->EdgeMapping.find(BB);
|
||||
if (EI != SDB->EdgeMapping.end())
|
||||
ThisBB = EI->second;
|
||||
for (MachineBasicBlock::iterator Phi = BB->begin();
|
||||
Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
|
||||
// This value for this PHI node is recorded in PHINodesToUpdate, get it.
|
||||
for (unsigned pn = 0; ; ++pn) {
|
||||
assert(pn != SDL->PHINodesToUpdate.size() &&
|
||||
assert(pn != SDB->PHINodesToUpdate.size() &&
|
||||
"Didn't find PHI entry!");
|
||||
if (SDL->PHINodesToUpdate[pn].first == Phi) {
|
||||
Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
|
||||
if (SDB->PHINodesToUpdate[pn].first == Phi) {
|
||||
Phi->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pn].
|
||||
second, false));
|
||||
Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
|
||||
break;
|
||||
@ -1045,19 +1045,19 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
}
|
||||
|
||||
// Don't process RHS if same block as LHS.
|
||||
if (BB == SDL->SwitchCases[i].FalseBB)
|
||||
SDL->SwitchCases[i].FalseBB = 0;
|
||||
if (BB == SDB->SwitchCases[i].FalseBB)
|
||||
SDB->SwitchCases[i].FalseBB = 0;
|
||||
|
||||
// If we haven't handled the RHS, do so now. Otherwise, we're done.
|
||||
SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
|
||||
SDL->SwitchCases[i].FalseBB = 0;
|
||||
SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
|
||||
SDB->SwitchCases[i].FalseBB = 0;
|
||||
}
|
||||
assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
|
||||
SDL->clear();
|
||||
assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
|
||||
SDB->clear();
|
||||
}
|
||||
SDL->SwitchCases.clear();
|
||||
SDB->SwitchCases.clear();
|
||||
|
||||
SDL->PHINodesToUpdate.clear();
|
||||
SDB->PHINodesToUpdate.clear();
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user