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Rename SelectionDAGLowering to SelectionDAGBuilder, and rename

Browse Source 
SelectionDAGBuild.cpp to SelectionDAGBuilder.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89681 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-11-23 18:04:58 +00:00
parent 131c4a5257
commit 2048b85c7c
6 changed files with 240 additions and 240 deletions
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4
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -23,7 +23,7 @@
namespace llvm { namespace llvm {
class FastISel; class FastISel;
class SelectionDAGLowering; class SelectionDAGBuilder;
class SDValue; class SDValue;
class MachineRegisterInfo; class MachineRegisterInfo;
class MachineBasicBlock; class MachineBasicBlock;
@ -48,7 +48,7 @@ public:
MachineFunction *MF; MachineFunction *MF;
MachineRegisterInfo *RegInfo; MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG; SelectionDAG *CurDAG;
SelectionDAGLowering *SDL; SelectionDAGBuilder *SDB;
MachineBasicBlock *BB; MachineBasicBlock *BB;
AliasAnalysis *AA; AliasAnalysis *AA;
GCFunctionInfo *GFI; GCFunctionInfo *GFI;

2
lib/CodeGen/SelectionDAG/CMakeLists.txt
View File

@ -16,7 +16,7 @@ add_llvm_library(LLVMSelectionDAG
ScheduleDAGRRList.cpp ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp ScheduleDAGSDNodes.cpp
SelectionDAG.cpp SelectionDAG.cpp
SelectionDAGBuild.cpp SelectionDAGBuilder.cpp
SelectionDAGISel.cpp SelectionDAGISel.cpp
SelectionDAGPrinter.cpp SelectionDAGPrinter.cpp
TargetLowering.cpp TargetLowering.cpp

2
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -54,7 +54,7 @@
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "SelectionDAGBuild.h" #include "SelectionDAGBuilder.h"
#include "FunctionLoweringInfo.h" #include "FunctionLoweringInfo.h"
using namespace llvm; using namespace llvm;

244
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp → lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -1,4 +1,4 @@
//===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===// //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#define DEBUG_TYPE "isel" #define DEBUG_TYPE "isel"
#include "SelectionDAGBuild.h" #include "SelectionDAGBuilder.h"
#include "FunctionLoweringInfo.h" #include "FunctionLoweringInfo.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
@ -501,19 +501,19 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
} }
void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
AA = &aa; AA = &aa;
GFI = gfi; GFI = gfi;
TD = DAG.getTarget().getTargetData(); TD = DAG.getTarget().getTargetData();
} }
/// clear - Clear out the curret SelectionDAG and the associated /// clear - Clear out the curret SelectionDAG and the associated
/// state and prepare this SelectionDAGLowering object to be used /// state and prepare this SelectionDAGBuilder object to be used
/// for a new block. This doesn't clear out information about /// for a new block. This doesn't clear out information about
/// additional blocks that are needed to complete switch lowering /// additional blocks that are needed to complete switch lowering
/// or PHI node updating; that information is cleared out as it is /// or PHI node updating; that information is cleared out as it is
/// consumed. /// consumed.
void SelectionDAGLowering::clear() { void SelectionDAGBuilder::clear() {
NodeMap.clear(); NodeMap.clear();
PendingLoads.clear(); PendingLoads.clear();
PendingExports.clear(); PendingExports.clear();
@ -528,7 +528,7 @@ void SelectionDAGLowering::clear() {
/// a store or any other node that may need to be ordered after any /// a store or any other node that may need to be ordered after any
/// prior load instructions. /// prior load instructions.
/// ///
SDValue SelectionDAGLowering::getRoot() { SDValue SelectionDAGBuilder::getRoot() {
if (PendingLoads.empty()) if (PendingLoads.empty())
return DAG.getRoot(); return DAG.getRoot();
@ -551,7 +551,7 @@ SDValue SelectionDAGLowering::getRoot() {
/// PendingLoad items, flush all the PendingExports items. It is necessary /// PendingLoad items, flush all the PendingExports items. It is necessary
/// to do this before emitting a terminator instruction. /// to do this before emitting a terminator instruction.
/// ///
SDValue SelectionDAGLowering::getControlRoot() { SDValue SelectionDAGBuilder::getControlRoot() {
SDValue Root = DAG.getRoot(); SDValue Root = DAG.getRoot();
if (PendingExports.empty()) if (PendingExports.empty())
@ -578,11 +578,11 @@ SDValue SelectionDAGLowering::getControlRoot() {
return Root; return Root;
} }
void SelectionDAGLowering::visit(Instruction &I) { void SelectionDAGBuilder::visit(Instruction &I) {
visit(I.getOpcode(), I); visit(I.getOpcode(), I);
} }
void SelectionDAGLowering::visit(unsigned Opcode, User &I) { void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
// Note: this doesn't use InstVisitor, because it has to work with // Note: this doesn't use InstVisitor, because it has to work with
// ConstantExpr's in addition to instructions. // ConstantExpr's in addition to instructions.
switch (Opcode) { switch (Opcode) {
@ -594,7 +594,7 @@ void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
} }
} }
SDValue SelectionDAGLowering::getValue(const Value *V) { SDValue SelectionDAGBuilder::getValue(const Value *V) {
SDValue &N = NodeMap[V]; SDValue &N = NodeMap[V];
if (N.getNode()) return N; if (N.getNode()) return N;
@ -759,7 +759,7 @@ static void getReturnInfo(const Type* ReturnType,
} }
} }
void SelectionDAGLowering::visitRet(ReturnInst &I) { void SelectionDAGBuilder::visitRet(ReturnInst &I) {
SDValue Chain = getControlRoot(); SDValue Chain = getControlRoot();
SmallVector<ISD::OutputArg, 8> Outs; SmallVector<ISD::OutputArg, 8> Outs;
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
@ -864,7 +864,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
/// CopyToExportRegsIfNeeded - If the given value has virtual registers /// CopyToExportRegsIfNeeded - If the given value has virtual registers
/// created for it, emit nodes to copy the value into the virtual /// created for it, emit nodes to copy the value into the virtual
/// registers. /// registers.
void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) { void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) {
if (!V->use_empty()) { if (!V->use_empty()) {
DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
if (VMI != FuncInfo.ValueMap.end()) if (VMI != FuncInfo.ValueMap.end())
@ -875,7 +875,7 @@ void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
/// ExportFromCurrentBlock - If this condition isn't known to be exported from /// ExportFromCurrentBlock - If this condition isn't known to be exported from
/// the current basic block, add it to ValueMap now so that we'll get a /// the current basic block, add it to ValueMap now so that we'll get a
/// CopyTo/FromReg. /// CopyTo/FromReg.
void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) {
// No need to export constants. // No need to export constants.
if (!isa<Instruction>(V) && !isa<Argument>(V)) return; if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
@ -886,8 +886,8 @@ void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
CopyValueToVirtualRegister(V, Reg); CopyValueToVirtualRegister(V, Reg);
} }
bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V,
const BasicBlock *FromBB) { const BasicBlock *FromBB) {
// The operands of the setcc have to be in this block. We don't know // The operands of the setcc have to be in this block. We don't know
// how to export them from some other block. // how to export them from some other block.
if (Instruction *VI = dyn_cast<Instruction>(V)) { if (Instruction *VI = dyn_cast<Instruction>(V)) {
@ -979,10 +979,10 @@ static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
/// AND operator tree. /// AND operator tree.
/// ///
void void
SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond, SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
MachineBasicBlock *CurBB) { MachineBasicBlock *CurBB) {
const BasicBlock *BB = CurBB->getBasicBlock(); const BasicBlock *BB = CurBB->getBasicBlock();
// If the leaf of the tree is a comparison, merge the condition into // If the leaf of the tree is a comparison, merge the condition into
@ -1018,11 +1018,11 @@ SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
} }
/// FindMergedConditions - If Cond is an expression like /// FindMergedConditions - If Cond is an expression like
void SelectionDAGLowering::FindMergedConditions(Value *Cond, void SelectionDAGBuilder::FindMergedConditions(Value *Cond,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
MachineBasicBlock *CurBB, MachineBasicBlock *CurBB,
unsigned Opc) { unsigned Opc) {
// If this node is not part of the or/and tree, emit it as a branch. // If this node is not part of the or/and tree, emit it as a branch.
Instruction *BOp = dyn_cast<Instruction>(Cond); Instruction *BOp = dyn_cast<Instruction>(Cond);
if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
@ -1077,7 +1077,7 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
/// If we should emit this as a bunch of and/or'd together conditions, return /// If we should emit this as a bunch of and/or'd together conditions, return
/// false. /// false.
bool bool
SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
if (Cases.size() != 2) return true; if (Cases.size() != 2) return true;
// If this is two comparisons of the same values or'd or and'd together, they // If this is two comparisons of the same values or'd or and'd together, they
@ -1092,7 +1092,7 @@ SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
return true; return true;
} }
void SelectionDAGLowering::visitBr(BranchInst &I) { void SelectionDAGBuilder::visitBr(BranchInst &I) {
// Update machine-CFG edges. // Update machine-CFG edges.
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
@ -1176,7 +1176,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
/// visitSwitchCase - Emits the necessary code to represent a single node in /// visitSwitchCase - Emits the necessary code to represent a single node in
/// the binary search tree resulting from lowering a switch instruction. /// the binary search tree resulting from lowering a switch instruction.
void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
SDValue Cond; SDValue Cond;
SDValue CondLHS = getValue(CB.CmpLHS); SDValue CondLHS = getValue(CB.CmpLHS);
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -1254,7 +1254,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
} }
/// visitJumpTable - Emit JumpTable node in the current MBB /// visitJumpTable - Emit JumpTable node in the current MBB
void SelectionDAGLowering::visitJumpTable(JumpTable &JT) { void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
// Emit the code for the jump table // Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!"); assert(JT.Reg != -1U && "Should lower JT Header first!");
EVT PTy = TLI.getPointerTy(); EVT PTy = TLI.getPointerTy();
@ -1268,8 +1268,8 @@ void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
/// visitJumpTableHeader - This function emits necessary code to produce index /// visitJumpTableHeader - This function emits necessary code to produce index
/// in the JumpTable from switch case. /// in the JumpTable from switch case.
void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
JumpTableHeader &JTH) { JumpTableHeader &JTH) {
// Subtract the lowest switch case value from the value being switched on and // Subtract the lowest switch case value from the value being switched on and
// conditional branch to default mbb if the result is greater than the // conditional branch to default mbb if the result is greater than the
// difference between smallest and largest cases. // difference between smallest and largest cases.
@ -1318,7 +1318,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
/// visitBitTestHeader - This function emits necessary code to produce value /// visitBitTestHeader - This function emits necessary code to produce value
/// suitable for "bit tests" /// suitable for "bit tests"
void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
// Subtract the minimum value // Subtract the minimum value
SDValue SwitchOp = getValue(B.SValue); SDValue SwitchOp = getValue(B.SValue);
EVT VT = SwitchOp.getValueType(); EVT VT = SwitchOp.getValueType();
@ -1361,9 +1361,9 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
} }
/// visitBitTestCase - this function produces one "bit test" /// visitBitTestCase - this function produces one "bit test"
void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
unsigned Reg, unsigned Reg,
BitTestCase &B) { BitTestCase &B) {
// Make desired shift // Make desired shift
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
TLI.getPointerTy()); TLI.getPointerTy());
@ -1402,7 +1402,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
DAG.getBasicBlock(NextMBB))); DAG.getBasicBlock(NextMBB)));
} }
void SelectionDAGLowering::visitInvoke(InvokeInst &I) { void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
// Retrieve successors. // Retrieve successors.
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
@ -1427,15 +1427,15 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
DAG.getBasicBlock(Return))); DAG.getBasicBlock(Return)));
} }
void SelectionDAGLowering::visitUnwind(UnwindInst &I) { void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
} }
/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
/// small case ranges). /// small case ranges).
bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
CaseRecVector& WorkList, CaseRecVector& WorkList,
Value* SV, Value* SV,
MachineBasicBlock* Default) { MachineBasicBlock* Default) {
Case& BackCase = *(CR.Range.second-1); Case& BackCase = *(CR.Range.second-1);
// Size is the number of Cases represented by this range. // Size is the number of Cases represented by this range.
@ -1529,10 +1529,10 @@ static APInt ComputeRange(const APInt &First, const APInt &Last) {
} }
/// handleJTSwitchCase - Emit jumptable for current switch case range /// handleJTSwitchCase - Emit jumptable for current switch case range
bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
CaseRecVector& WorkList, CaseRecVector& WorkList,
Value* SV, Value* SV,
MachineBasicBlock* Default) { MachineBasicBlock* Default) {
Case& FrontCase = *CR.Range.first; Case& FrontCase = *CR.Range.first;
Case& BackCase = *(CR.Range.second-1); Case& BackCase = *(CR.Range.second-1);
@ -1623,10 +1623,10 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
/// handleBTSplitSwitchCase - emit comparison and split binary search tree into /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
/// 2 subtrees. /// 2 subtrees.
bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
CaseRecVector& WorkList, CaseRecVector& WorkList,
Value* SV, Value* SV,
MachineBasicBlock* Default) { MachineBasicBlock* Default) {
// Get the MachineFunction which holds the current MBB. This is used when // Get the MachineFunction which holds the current MBB. This is used when
// inserting any additional MBBs necessary to represent the switch. // inserting any additional MBBs necessary to represent the switch.
MachineFunction *CurMF = FuncInfo.MF; MachineFunction *CurMF = FuncInfo.MF;
@ -1751,10 +1751,10 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
/// handleBitTestsSwitchCase - if current case range has few destination and /// handleBitTestsSwitchCase - if current case range has few destination and
/// range span less, than machine word bitwidth, encode case range into series /// range span less, than machine word bitwidth, encode case range into series
/// of masks and emit bit tests with these masks. /// of masks and emit bit tests with these masks.
bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
CaseRecVector& WorkList, CaseRecVector& WorkList,
Value* SV, Value* SV,
MachineBasicBlock* Default){ MachineBasicBlock* Default){
EVT PTy = TLI.getPointerTy(); EVT PTy = TLI.getPointerTy();
unsigned IntPtrBits = PTy.getSizeInBits(); unsigned IntPtrBits = PTy.getSizeInBits();
@ -1882,8 +1882,8 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
/// Clusterify - Transform simple list of Cases into list of CaseRange's /// Clusterify - Transform simple list of Cases into list of CaseRange's
size_t SelectionDAGLowering::Clusterify(CaseVector& Cases, size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
const SwitchInst& SI) { const SwitchInst& SI) {
size_t numCmps = 0; size_t numCmps = 0;
// Start with "simple" cases // Start with "simple" cases
@ -1924,7 +1924,7 @@ size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
return numCmps; return numCmps;
} }
void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
// Figure out which block is immediately after the current one. // Figure out which block is immediately after the current one.
MachineBasicBlock *NextBlock = 0; MachineBasicBlock *NextBlock = 0;
@ -1987,7 +1987,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
} }
} }
void SelectionDAGLowering::visitIndirectBr(IndirectBrInst &I) { void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
// Update machine-CFG edges. // Update machine-CFG edges.
for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]); CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);
@ -1998,7 +1998,7 @@ void SelectionDAGLowering::visitIndirectBr(IndirectBrInst &I) {
} }
void SelectionDAGLowering::visitFSub(User &I) { void SelectionDAGBuilder::visitFSub(User &I) {
// -0.0 - X --> fneg // -0.0 - X --> fneg
const Type *Ty = I.getType(); const Type *Ty = I.getType();
if (isa<VectorType>(Ty)) { if (isa<VectorType>(Ty)) {
@ -2027,7 +2027,7 @@ void SelectionDAGLowering::visitFSub(User &I) {
visitBinary(I, ISD::FSUB); visitBinary(I, ISD::FSUB);
} }
void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
SDValue Op1 = getValue(I.getOperand(0)); SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1)); SDValue Op2 = getValue(I.getOperand(1));
@ -2035,7 +2035,7 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
Op1.getValueType(), Op1, Op2)); Op1.getValueType(), Op1, Op2));
} }
void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
SDValue Op1 = getValue(I.getOperand(0)); SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1)); SDValue Op2 = getValue(I.getOperand(1));
if (!isa<VectorType>(I.getType()) && if (!isa<VectorType>(I.getType()) &&
@ -2069,7 +2069,7 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
Op1.getValueType(), Op1, Op2)); Op1.getValueType(), Op1, Op2));
} }
void SelectionDAGLowering::visitICmp(User &I) { void SelectionDAGBuilder::visitICmp(User &I) {
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
predicate = IC->getPredicate(); predicate = IC->getPredicate();
@ -2083,7 +2083,7 @@ void SelectionDAGLowering::visitICmp(User &I) {
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
} }
void SelectionDAGLowering::visitFCmp(User &I) { void SelectionDAGBuilder::visitFCmp(User &I) {
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
predicate = FC->getPredicate(); predicate = FC->getPredicate();
@ -2096,7 +2096,7 @@ void SelectionDAGLowering::visitFCmp(User &I) {
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
} }
void SelectionDAGLowering::visitSelect(User &I) { void SelectionDAGBuilder::visitSelect(User &I) {
SmallVector<EVT, 4> ValueVTs; SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs); ComputeValueVTs(TLI, I.getType(), ValueVTs);
unsigned NumValues = ValueVTs.size(); unsigned NumValues = ValueVTs.size();
@ -2119,14 +2119,14 @@ void SelectionDAGLowering::visitSelect(User &I) {
} }
void SelectionDAGLowering::visitTrunc(User &I) { void SelectionDAGBuilder::visitTrunc(User &I) {
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitZExt(User &I) { void SelectionDAGBuilder::visitZExt(User &I) {
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// ZExt also can't be a cast to bool for same reason. So, nothing much to do // ZExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
@ -2134,7 +2134,7 @@ void SelectionDAGLowering::visitZExt(User &I) {
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitSExt(User &I) { void SelectionDAGBuilder::visitSExt(User &I) {
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// SExt also can't be a cast to bool for same reason. So, nothing much to do // SExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
@ -2142,7 +2142,7 @@ void SelectionDAGLowering::visitSExt(User &I) {
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitFPTrunc(User &I) { void SelectionDAGBuilder::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check // FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
@ -2150,42 +2150,42 @@ void SelectionDAGLowering::visitFPTrunc(User &I) {
DestVT, N, DAG.getIntPtrConstant(0))); DestVT, N, DAG.getIntPtrConstant(0)));
} }
void SelectionDAGLowering::visitFPExt(User &I){ void SelectionDAGBuilder::visitFPExt(User &I){
// FPTrunc is never a no-op cast, no need to check // FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitFPToUI(User &I) { void SelectionDAGBuilder::visitFPToUI(User &I) {
// FPToUI is never a no-op cast, no need to check // FPToUI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitFPToSI(User &I) { void SelectionDAGBuilder::visitFPToSI(User &I) {
// FPToSI is never a no-op cast, no need to check // FPToSI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitUIToFP(User &I) { void SelectionDAGBuilder::visitUIToFP(User &I) {
// UIToFP is never a no-op cast, no need to check // UIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitSIToFP(User &I){ void SelectionDAGBuilder::visitSIToFP(User &I){
// SIToFP is never a no-op cast, no need to check // SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
} }
void SelectionDAGLowering::visitPtrToInt(User &I) { void SelectionDAGBuilder::visitPtrToInt(User &I) {
// What to do depends on the size of the integer and the size of the pointer. // What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly. // We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
@ -2195,7 +2195,7 @@ void SelectionDAGLowering::visitPtrToInt(User &I) {
setValue(&I, Result); setValue(&I, Result);
} }
void SelectionDAGLowering::visitIntToPtr(User &I) { void SelectionDAGBuilder::visitIntToPtr(User &I) {
// What to do depends on the size of the integer and the size of the pointer. // What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly. // We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
@ -2204,7 +2204,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) {
setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
} }
void SelectionDAGLowering::visitBitCast(User &I) { void SelectionDAGBuilder::visitBitCast(User &I) {
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
@ -2217,7 +2217,7 @@ void SelectionDAGLowering::visitBitCast(User &I) {
setValue(&I, N); // noop cast. setValue(&I, N); // noop cast.
} }
void SelectionDAGLowering::visitInsertElement(User &I) { void SelectionDAGBuilder::visitInsertElement(User &I) {
SDValue InVec = getValue(I.getOperand(0)); SDValue InVec = getValue(I.getOperand(0));
SDValue InVal = getValue(I.getOperand(1)); SDValue InVal = getValue(I.getOperand(1));
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
@ -2229,7 +2229,7 @@ void SelectionDAGLowering::visitInsertElement(User &I) {
InVec, InVal, InIdx)); InVec, InVal, InIdx));
} }
void SelectionDAGLowering::visitExtractElement(User &I) { void SelectionDAGBuilder::visitExtractElement(User &I) {
SDValue InVec = getValue(I.getOperand(0)); SDValue InVec = getValue(I.getOperand(0));
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), TLI.getPointerTy(),
@ -2249,7 +2249,7 @@ static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
return true; return true;
} }
void SelectionDAGLowering::visitShuffleVector(User &I) { void SelectionDAGBuilder::visitShuffleVector(User &I) {
SmallVector<int, 8> Mask; SmallVector<int, 8> Mask;
SDValue Src1 = getValue(I.getOperand(0)); SDValue Src1 = getValue(I.getOperand(0));
SDValue Src2 = getValue(I.getOperand(1)); SDValue Src2 = getValue(I.getOperand(1));
@ -2423,7 +2423,7 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
VT, &Ops[0], Ops.size())); VT, &Ops[0], Ops.size()));
} }
void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) {
const Value *Op0 = I.getOperand(0); const Value *Op0 = I.getOperand(0);
const Value *Op1 = I.getOperand(1); const Value *Op1 = I.getOperand(1);
const Type *AggTy = I.getType(); const Type *AggTy = I.getType();
@ -2464,7 +2464,7 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
&Values[0], NumAggValues)); &Values[0], NumAggValues));
} }
void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) {
const Value *Op0 = I.getOperand(0); const Value *Op0 = I.getOperand(0);
const Type *AggTy = Op0->getType(); const Type *AggTy = Op0->getType();
const Type *ValTy = I.getType(); const Type *ValTy = I.getType();
@ -2493,7 +2493,7 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
} }
void SelectionDAGLowering::visitGetElementPtr(User &I) { void SelectionDAGBuilder::visitGetElementPtr(User &I) {
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
const Type *Ty = I.getOperand(0)->getType(); const Type *Ty = I.getOperand(0)->getType();
@ -2562,7 +2562,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
setValue(&I, N); setValue(&I, N);
} }
void SelectionDAGLowering::visitAlloca(AllocaInst &I) { void SelectionDAGBuilder::visitAlloca(AllocaInst &I) {
// If this is a fixed sized alloca in the entry block of the function, // If this is a fixed sized alloca in the entry block of the function,
// allocate it statically on the stack. // allocate it statically on the stack.
if (FuncInfo.StaticAllocaMap.count(&I)) if (FuncInfo.StaticAllocaMap.count(&I))
@ -2615,7 +2615,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(); FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
} }
void SelectionDAGLowering::visitLoad(LoadInst &I) { void SelectionDAGBuilder::visitLoad(LoadInst &I) {
const Value *SV = I.getOperand(0); const Value *SV = I.getOperand(0);
SDValue Ptr = getValue(SV); SDValue Ptr = getValue(SV);
@ -2673,7 +2673,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
} }
void SelectionDAGLowering::visitStore(StoreInst &I) { void SelectionDAGBuilder::visitStore(StoreInst &I) {
Value *SrcV = I.getOperand(0); Value *SrcV = I.getOperand(0);
Value *PtrV = I.getOperand(1); Value *PtrV = I.getOperand(1);
@ -2709,8 +2709,8 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
/// node. /// node.
void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
unsigned Intrinsic) { unsigned Intrinsic) {
bool HasChain = !I.doesNotAccessMemory(); bool HasChain = !I.doesNotAccessMemory();
bool OnlyLoad = HasChain && I.onlyReadsMemory(); bool OnlyLoad = HasChain && I.onlyReadsMemory();
@ -2832,7 +2832,7 @@ getF32Constant(SelectionDAG &DAG, unsigned Flt) {
/// visitIntrinsicCall: I is a call instruction /// visitIntrinsicCall: I is a call instruction
/// Op is the associated NodeType for I /// Op is the associated NodeType for I
const char * const char *
SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
SDValue Root = getRoot(); SDValue Root = getRoot();
SDValue L = SDValue L =
DAG.getAtomic(Op, getCurDebugLoc(), DAG.getAtomic(Op, getCurDebugLoc(),
@ -2848,7 +2848,7 @@ SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
// implVisitAluOverflow - Lower arithmetic overflow instrinsics. // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
const char * const char *
SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) { SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
SDValue Op1 = getValue(I.getOperand(1)); SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2)); SDValue Op2 = getValue(I.getOperand(2));
@ -2862,7 +2862,7 @@ SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
/// visitExp - Lower an exp intrinsic. Handles the special sequences for /// visitExp - Lower an exp intrinsic. Handles the special sequences for
/// limited-precision mode. /// limited-precision mode.
void void
SelectionDAGLowering::visitExp(CallInst &I) { SelectionDAGBuilder::visitExp(CallInst &I) {
SDValue result; SDValue result;
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -2988,7 +2988,7 @@ SelectionDAGLowering::visitExp(CallInst &I) {
/// visitLog - Lower a log intrinsic. Handles the special sequences for /// visitLog - Lower a log intrinsic. Handles the special sequences for
/// limited-precision mode. /// limited-precision mode.
void void
SelectionDAGLowering::visitLog(CallInst &I) { SelectionDAGBuilder::visitLog(CallInst &I) {
SDValue result; SDValue result;
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -3098,7 +3098,7 @@ SelectionDAGLowering::visitLog(CallInst &I) {
/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
/// limited-precision mode. /// limited-precision mode.
void void
SelectionDAGLowering::visitLog2(CallInst &I) { SelectionDAGBuilder::visitLog2(CallInst &I) {
SDValue result; SDValue result;
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -3207,7 +3207,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
/// limited-precision mode. /// limited-precision mode.
void void
SelectionDAGLowering::visitLog10(CallInst &I) { SelectionDAGBuilder::visitLog10(CallInst &I) {
SDValue result; SDValue result;
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -3309,7 +3309,7 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
/// limited-precision mode. /// limited-precision mode.
void void
SelectionDAGLowering::visitExp2(CallInst &I) { SelectionDAGBuilder::visitExp2(CallInst &I) {
SDValue result; SDValue result;
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -3423,7 +3423,7 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
/// visitPow - Lower a pow intrinsic. Handles the special sequences for /// visitPow - Lower a pow intrinsic. Handles the special sequences for
/// limited-precision mode with x == 10.0f. /// limited-precision mode with x == 10.0f.
void void
SelectionDAGLowering::visitPow(CallInst &I) { SelectionDAGBuilder::visitPow(CallInst &I) {
SDValue result; SDValue result;
Value *Val = I.getOperand(1); Value *Val = I.getOperand(1);
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
@ -3558,7 +3558,7 @@ SelectionDAGLowering::visitPow(CallInst &I) {
/// we want to emit this as a call to a named external function, return the name /// we want to emit this as a call to a named external function, return the name
/// otherwise lower it and return null. /// otherwise lower it and return null.
const char * const char *
SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
DebugLoc dl = getCurDebugLoc(); DebugLoc dl = getCurDebugLoc();
switch (Intrinsic) { switch (Intrinsic) {
default: default:
@ -4123,9 +4123,9 @@ isInTailCallPosition(const Instruction *I, Attributes CalleeRetAttr,
return true; return true;
} }
void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
bool isTailCall, bool isTailCall,
MachineBasicBlock *LandingPad) { MachineBasicBlock *LandingPad) {
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
const Type *RetTy = FTy->getReturnType(); const Type *RetTy = FTy->getReturnType();
@ -4272,7 +4272,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
} }
void SelectionDAGLowering::visitCall(CallInst &I) { void SelectionDAGBuilder::visitCall(CallInst &I) {
const char *RenameFn = 0; const char *RenameFn = 0;
if (Function *F = I.getCalledFunction()) { if (Function *F = I.getCalledFunction()) {
if (F->isDeclaration()) { if (F->isDeclaration()) {
@ -4667,7 +4667,7 @@ private:
/// OpInfo describes the operand. /// OpInfo describes the operand.
/// Input and OutputRegs are the set of already allocated physical registers. /// Input and OutputRegs are the set of already allocated physical registers.
/// ///
void SelectionDAGLowering:: void SelectionDAGBuilder::
GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
std::set<unsigned> &OutputRegs, std::set<unsigned> &OutputRegs,
std::set<unsigned> &InputRegs) { std::set<unsigned> &InputRegs) {
@ -4861,7 +4861,7 @@ hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
/// visitInlineAsm - Handle a call to an InlineAsm object. /// visitInlineAsm - Handle a call to an InlineAsm object.
/// ///
void SelectionDAGLowering::visitInlineAsm(CallSite CS) { void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
/// ConstraintOperands - Information about all of the constraints. /// ConstraintOperands - Information about all of the constraints.
@ -5283,14 +5283,14 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
DAG.setRoot(Chain); DAG.setRoot(Chain);
} }
void SelectionDAGLowering::visitVAStart(CallInst &I) { void SelectionDAGBuilder::visitVAStart(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
MVT::Other, getRoot(), MVT::Other, getRoot(),
getValue(I.getOperand(1)), getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1)))); DAG.getSrcValue(I.getOperand(1))));
} }
void SelectionDAGLowering::visitVAArg(VAArgInst &I) { void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
getRoot(), getValue(I.getOperand(0)), getRoot(), getValue(I.getOperand(0)),
DAG.getSrcValue(I.getOperand(0))); DAG.getSrcValue(I.getOperand(0)));
@ -5298,14 +5298,14 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
DAG.setRoot(V.getValue(1)); DAG.setRoot(V.getValue(1));
} }
void SelectionDAGLowering::visitVAEnd(CallInst &I) { void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
MVT::Other, getRoot(), MVT::Other, getRoot(),
getValue(I.getOperand(1)), getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1)))); DAG.getSrcValue(I.getOperand(1))));
} }
void SelectionDAGLowering::visitVACopy(CallInst &I) { void SelectionDAGBuilder::visitVACopy(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
MVT::Other, getRoot(), MVT::Other, getRoot(),
getValue(I.getOperand(1)), getValue(I.getOperand(1)),
@ -5498,7 +5498,7 @@ SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
} }
void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) { void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
SDValue Op = getValue(V); SDValue Op = getValue(V);
assert((Op.getOpcode() != ISD::CopyFromReg || assert((Op.getOpcode() != ISD::CopyFromReg ||
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
@ -5516,9 +5516,9 @@ void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) { void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
// If this is the entry block, emit arguments. // If this is the entry block, emit arguments.
Function &F = *LLVMBB->getParent(); Function &F = *LLVMBB->getParent();
SelectionDAG &DAG = SDL->DAG; SelectionDAG &DAG = SDB->DAG;
SDValue OldRoot = DAG.getRoot(); SDValue OldRoot = DAG.getRoot();
DebugLoc dl = SDL->getCurDebugLoc(); DebugLoc dl = SDB->getCurDebugLoc();
const TargetData *TD = TLI.getTargetData(); const TargetData *TD = TLI.getTargetData();
SmallVector<ISD::InputArg, 16> Ins; SmallVector<ISD::InputArg, 16> Ins;
@ -5634,11 +5634,11 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT,
VT, AssertOp); VT, AssertOp);
MachineFunction& MF = SDL->DAG.getMachineFunction(); MachineFunction& MF = SDB->DAG.getMachineFunction();
MachineRegisterInfo& RegInfo = MF.getRegInfo(); MachineRegisterInfo& RegInfo = MF.getRegInfo();
unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
FLI.DemoteRegister = SRetReg; FLI.DemoteRegister = SRetReg;
NewRoot = SDL->DAG.getCopyToReg(NewRoot, SDL->getCurDebugLoc(), SRetReg, ArgValue); NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), SRetReg, ArgValue);
DAG.setRoot(NewRoot); DAG.setRoot(NewRoot);
// i indexes lowered arguments. Bump it past the hidden sret argument. // i indexes lowered arguments. Bump it past the hidden sret argument.
@ -5669,18 +5669,18 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
i += NumParts; i += NumParts;
} }
if (!I->use_empty()) { if (!I->use_empty()) {
SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues, SDB->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
SDL->getCurDebugLoc())); SDB->getCurDebugLoc()));
// If this argument is live outside of the entry block, insert a copy from // If this argument is live outside of the entry block, insert a copy from
// whereever we got it to the vreg that other BB's will reference it as. // whereever we got it to the vreg that other BB's will reference it as.
SDL->CopyToExportRegsIfNeeded(I); SDB->CopyToExportRegsIfNeeded(I);
} }
} }
assert(i == InVals.size() && "Argument register count mismatch!"); assert(i == InVals.size() && "Argument register count mismatch!");
// Finally, if the target has anything special to do, allow it to do so. // Finally, if the target has anything special to do, allow it to do so.
// FIXME: this should insert code into the DAG! // FIXME: this should insert code into the DAG!
EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction()); EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction());
} }
/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
@ -5722,10 +5722,10 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
if (Constant *C = dyn_cast<Constant>(PHIOp)) { if (Constant *C = dyn_cast<Constant>(PHIOp)) {
unsigned &RegOut = SDL->ConstantsOut[C]; unsigned &RegOut = SDB->ConstantsOut[C];
if (RegOut == 0) { if (RegOut == 0) {
RegOut = FuncInfo->CreateRegForValue(C); RegOut = FuncInfo->CreateRegForValue(C);
SDL->CopyValueToVirtualRegister(C, RegOut); SDB->CopyValueToVirtualRegister(C, RegOut);
} }
Reg = RegOut; Reg = RegOut;
} else { } else {
@ -5735,7 +5735,7 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
"Didn't codegen value into a register!??"); "Didn't codegen value into a register!??");
Reg = FuncInfo->CreateRegForValue(PHIOp); Reg = FuncInfo->CreateRegForValue(PHIOp);
SDL->CopyValueToVirtualRegister(PHIOp, Reg); SDB->CopyValueToVirtualRegister(PHIOp, Reg);
} }
} }
@ -5747,12 +5747,12 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
EVT VT = ValueVTs[vti]; EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT); unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
for (unsigned i = 0, e = NumRegisters; i != e; ++i) for (unsigned i = 0, e = NumRegisters; i != e; ++i)
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
Reg += NumRegisters; Reg += NumRegisters;
} }
} }
} }
SDL->ConstantsOut.clear(); SDB->ConstantsOut.clear();
} }
/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
@ -5765,7 +5765,7 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
TerminatorInst *TI = LLVMBB->getTerminator(); TerminatorInst *TI = LLVMBB->getTerminator();
SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size(); unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
// Check successor nodes' PHI nodes that expect a constant to be available // Check successor nodes' PHI nodes that expect a constant to be available
// from this block. // from this block.
@ -5801,7 +5801,7 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
if (VT == MVT::i1) if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT); VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
else { else {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
return false; return false;
} }
} }
@ -5810,10 +5810,10 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
unsigned Reg = F->getRegForValue(PHIOp); unsigned Reg = F->getRegForValue(PHIOp);
if (Reg == 0) { if (Reg == 0) {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
return false; return false;
} }
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
} }
} }

24
lib/CodeGen/SelectionDAG/SelectionDAGBuild.h → lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -1,4 +1,4 @@
//===-- SelectionDAGBuild.h - Selection-DAG building ----------------------===// //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@ -11,8 +11,8 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef SELECTIONDAGBUILD_H #ifndef SELECTIONDAGBUILDER_H
#define SELECTIONDAGBUILD_H #define SELECTIONDAGBUILDER_H
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
@ -79,11 +79,11 @@ class VAArgInst;
class ZExtInst; class ZExtInst;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// SelectionDAGLowering - This is the common target-independent lowering /// SelectionDAGBuilder - This is the common target-independent lowering
/// implementation that is parameterized by a TargetLowering object. /// implementation that is parameterized by a TargetLowering object.
/// Also, targets can overload any lowering method. /// Also, targets can overload any lowering method.
/// ///
class SelectionDAGLowering { class SelectionDAGBuilder {
MachineBasicBlock *CurMBB; MachineBasicBlock *CurMBB;
/// CurDebugLoc - current file + line number. Changes as we build the DAG. /// CurDebugLoc - current file + line number. Changes as we build the DAG.
@ -173,9 +173,9 @@ class SelectionDAGLowering {
size_t Clusterify(CaseVector& Cases, const SwitchInst &SI); size_t Clusterify(CaseVector& Cases, const SwitchInst &SI);
/// CaseBlock - This structure is used to communicate between SDLowering and /// CaseBlock - This structure is used to communicate between
/// SDISel for the code generation of additional basic blocks needed by multi- /// SelectionDAGBuilder and SDISel for the code generation of additional basic
/// case switch statements. /// blocks needed by multi-case switch statements.
struct CaseBlock { struct CaseBlock {
CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle, CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
MachineBasicBlock *truebb, MachineBasicBlock *falsebb, MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
@ -297,9 +297,9 @@ public:
LLVMContext *Context; LLVMContext *Context;
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, SelectionDAGBuilder(SelectionDAG &dag, TargetLowering &tli,
FunctionLoweringInfo &funcinfo, FunctionLoweringInfo &funcinfo,
CodeGenOpt::Level ol) CodeGenOpt::Level ol)
: CurDebugLoc(DebugLoc::getUnknownLoc()), : CurDebugLoc(DebugLoc::getUnknownLoc()),
TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol), TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
HasTailCall(false), HasTailCall(false),
@ -309,7 +309,7 @@ public:
void init(GCFunctionInfo *gfi, AliasAnalysis &aa); void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
/// clear - Clear out the curret SelectionDAG and the associated /// clear - Clear out the curret SelectionDAG and the associated
/// state and prepare this SelectionDAGLowering object to be used /// state and prepare this SelectionDAGBuilder object to be used
/// for a new block. This doesn't clear out information about /// for a new block. This doesn't clear out information about
/// additional blocks that are needed to complete switch lowering /// additional blocks that are needed to complete switch lowering
/// or PHI node updating; that information is cleared out as it is /// or PHI node updating; that information is cleared out as it is

204
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -13,7 +13,7 @@
#define DEBUG_TYPE "isel" #define DEBUG_TYPE "isel"
#include "ScheduleDAGSDNodes.h" #include "ScheduleDAGSDNodes.h"
#include "SelectionDAGBuild.h" #include "SelectionDAGBuilder.h"
#include "FunctionLoweringInfo.h" #include "FunctionLoweringInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/AliasAnalysis.h"
@ -280,14 +280,14 @@ SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
FuncInfo(new FunctionLoweringInfo(TLI)), FuncInfo(new FunctionLoweringInfo(TLI)),
CurDAG(new SelectionDAG(TLI, *FuncInfo)), CurDAG(new SelectionDAG(TLI, *FuncInfo)),
SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)), SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
GFI(), GFI(),
OptLevel(OL), OptLevel(OL),
DAGSize(0) DAGSize(0)
{} {}
SelectionDAGISel::~SelectionDAGISel() { SelectionDAGISel::~SelectionDAGISel() {
delete SDL; delete SDB;
delete CurDAG; delete CurDAG;
delete FuncInfo; delete FuncInfo;
} }
@ -333,7 +333,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
CurDAG->init(*MF, MMI, DW); CurDAG->init(*MF, MMI, DW);
FuncInfo->set(Fn, *MF, EnableFastISel); FuncInfo->set(Fn, *MF, EnableFastISel);
SDL->init(GFI, *AA); SDB->init(GFI, *AA);
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
@ -379,13 +379,13 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
BasicBlock::iterator Begin, BasicBlock::iterator Begin,
BasicBlock::iterator End, BasicBlock::iterator End,
bool &HadTailCall) { bool &HadTailCall) {
SDL->setCurrentBasicBlock(BB); SDB->setCurrentBasicBlock(BB);
MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata();
unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
// Lower all of the non-terminator instructions. If a call is emitted // Lower all of the non-terminator instructions. If a call is emitted
// as a tail call, cease emitting nodes for this block. // as a tail call, cease emitting nodes for this block.
for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) { for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
if (MDDbgKind) { if (MDDbgKind) {
// Update DebugLoc if debug information is attached with this // Update DebugLoc if debug information is attached with this
// instruction. // instruction.
@ -393,38 +393,38 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) { if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) {
DILocation DILoc(Dbg); DILocation DILoc(Dbg);
DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
SDL->setCurDebugLoc(Loc); SDB->setCurDebugLoc(Loc);
if (MF->getDefaultDebugLoc().isUnknown()) if (MF->getDefaultDebugLoc().isUnknown())
MF->setDefaultDebugLoc(Loc); MF->setDefaultDebugLoc(Loc);
} }
} }
if (!isa<TerminatorInst>(I)) if (!isa<TerminatorInst>(I))
SDL->visit(*I); SDB->visit(*I);
} }
if (!SDL->HasTailCall) { if (!SDB->HasTailCall) {
// Ensure that all instructions which are used outside of their defining // Ensure that all instructions which are used outside of their defining
// blocks are available as virtual registers. Invoke is handled elsewhere. // blocks are available as virtual registers. Invoke is handled elsewhere.
for (BasicBlock::iterator I = Begin; I != End; ++I) for (BasicBlock::iterator I = Begin; I != End; ++I)
if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
SDL->CopyToExportRegsIfNeeded(I); SDB->CopyToExportRegsIfNeeded(I);
// Handle PHI nodes in successor blocks. // Handle PHI nodes in successor blocks.
if (End == LLVMBB->end()) { if (End == LLVMBB->end()) {
HandlePHINodesInSuccessorBlocks(LLVMBB); HandlePHINodesInSuccessorBlocks(LLVMBB);
// Lower the terminator after the copies are emitted. // Lower the terminator after the copies are emitted.
SDL->visit(*LLVMBB->getTerminator()); SDB->visit(*LLVMBB->getTerminator());
} }
} }
// Make sure the root of the DAG is up-to-date. // Make sure the root of the DAG is up-to-date.
CurDAG->setRoot(SDL->getControlRoot()); CurDAG->setRoot(SDB->getControlRoot());
// Final step, emit the lowered DAG as machine code. // Final step, emit the lowered DAG as machine code.
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
HadTailCall = SDL->HasTailCall; HadTailCall = SDB->HasTailCall;
SDL->clear(); SDB->clear();
} }
void SelectionDAGISel::ComputeLiveOutVRegInfo() { void SelectionDAGISel::ComputeLiveOutVRegInfo() {
@ -632,9 +632,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
// inserted into. // inserted into.
if (TimePassesIsEnabled) { if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Creation", GroupName); NamedRegionTimer T("Instruction Creation", GroupName);
BB = Scheduler->EmitSchedule(&SDL->EdgeMapping); BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
} else { } else {
BB = Scheduler->EmitSchedule(&SDL->EdgeMapping); BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
} }
// Free the scheduler state. // Free the scheduler state.
@ -704,7 +704,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
unsigned LabelID = MMI->addLandingPad(BB); unsigned LabelID = MMI->addLandingPad(BB);
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID); BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
// Mark exception register as live in. // Mark exception register as live in.
unsigned Reg = TLI.getExceptionAddressRegister(); unsigned Reg = TLI.getExceptionAddressRegister();
@ -744,9 +744,9 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
// Emit code for any incoming arguments. This must happen before // Emit code for any incoming arguments. This must happen before
// beginning FastISel on the entry block. // beginning FastISel on the entry block.
if (LLVMBB == &Fn.getEntryBlock()) { if (LLVMBB == &Fn.getEntryBlock()) {
CurDAG->setRoot(SDL->getControlRoot()); CurDAG->setRoot(SDB->getControlRoot());
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
SDL->clear(); SDB->clear();
} }
FastIS->startNewBlock(BB); FastIS->startNewBlock(BB);
// Do FastISel on as many instructions as possible. // Do FastISel on as many instructions as possible.
@ -799,7 +799,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
R = FuncInfo->CreateRegForValue(BI); R = FuncInfo->CreateRegForValue(BI);
} }
SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); SDB->setCurDebugLoc(FastIS->getCurDebugLoc());
bool HadTailCall = false; bool HadTailCall = false;
SelectBasicBlock(LLVMBB, BI, next(BI), HadTailCall); SelectBasicBlock(LLVMBB, BI, next(BI), HadTailCall);
@ -838,7 +838,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
if (BI != End) { if (BI != End) {
// If FastISel is run and it has known DebugLoc then use it. // If FastISel is run and it has known DebugLoc then use it.
if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) if (FastIS && !FastIS->getCurDebugLoc().isUnknown())
SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); SDB->setCurDebugLoc(FastIS->getCurDebugLoc());
bool HadTailCall; bool HadTailCall;
SelectBasicBlock(LLVMBB, BI, End, HadTailCall); SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
} }
@ -856,150 +856,150 @@ SelectionDAGISel::FinishBasicBlock() {
DEBUG(BB->dump()); DEBUG(BB->dump());
DEBUG(errs() << "Total amount of phi nodes to update: " DEBUG(errs() << "Total amount of phi nodes to update: "
<< SDL->PHINodesToUpdate.size() << "\n"); << SDB->PHINodesToUpdate.size() << "\n");
DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
errs() << "Node " << i << " : (" errs() << "Node " << i << " : ("
<< SDL->PHINodesToUpdate[i].first << SDB->PHINodesToUpdate[i].first
<< ", " << SDL->PHINodesToUpdate[i].second << ")\n"); << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
// Next, now that we know what the last MBB the LLVM BB expanded is, update // Next, now that we know what the last MBB the LLVM BB expanded is, update
// PHI nodes in successors. // PHI nodes in successors.
if (SDL->SwitchCases.empty() && if (SDB->SwitchCases.empty() &&
SDL->JTCases.empty() && SDB->JTCases.empty() &&
SDL->BitTestCases.empty()) { SDB->BitTestCases.empty()) {
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
false)); false));
PHI->addOperand(MachineOperand::CreateMBB(BB)); PHI->addOperand(MachineOperand::CreateMBB(BB));
} }
SDL->PHINodesToUpdate.clear(); SDB->PHINodesToUpdate.clear();
return; return;
} }
for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
// Lower header first, if it wasn't already lowered // Lower header first, if it wasn't already lowered
if (!SDL->BitTestCases[i].Emitted) { if (!SDB->BitTestCases[i].Emitted) {
// Set the current basic block to the mbb we wish to insert the code into // Set the current basic block to the mbb we wish to insert the code into
BB = SDL->BitTestCases[i].Parent; BB = SDB->BitTestCases[i].Parent;
SDL->setCurrentBasicBlock(BB); SDB->setCurrentBasicBlock(BB);
// Emit the code // Emit the code
SDL->visitBitTestHeader(SDL->BitTestCases[i]); SDB->visitBitTestHeader(SDB->BitTestCases[i]);
CurDAG->setRoot(SDL->getRoot()); CurDAG->setRoot(SDB->getRoot());
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
SDL->clear(); SDB->clear();
} }
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
// Set the current basic block to the mbb we wish to insert the code into // Set the current basic block to the mbb we wish to insert the code into
BB = SDL->BitTestCases[i].Cases[j].ThisBB; BB = SDB->BitTestCases[i].Cases[j].ThisBB;
SDL->setCurrentBasicBlock(BB); SDB->setCurrentBasicBlock(BB);
// Emit the code // Emit the code
if (j+1 != ej) if (j+1 != ej)
SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
SDL->BitTestCases[i].Reg, SDB->BitTestCases[i].Reg,
SDL->BitTestCases[i].Cases[j]); SDB->BitTestCases[i].Cases[j]);
else else
SDL->visitBitTestCase(SDL->BitTestCases[i].Default, SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
SDL->BitTestCases[i].Reg, SDB->BitTestCases[i].Reg,
SDL->BitTestCases[i].Cases[j]); SDB->BitTestCases[i].Cases[j]);
CurDAG->setRoot(SDL->getRoot()); CurDAG->setRoot(SDB->getRoot());
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
SDL->clear(); SDB->clear();
} }
// Update PHI Nodes // Update PHI Nodes
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
MachineBasicBlock *PHIBB = PHI->getParent(); MachineBasicBlock *PHIBB = PHI->getParent();
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
// This is "default" BB. We have two jumps to it. From "header" BB and // This is "default" BB. We have two jumps to it. From "header" BB and
// from last "case" BB. // from last "case" BB.
if (PHIBB == SDL->BitTestCases[i].Default) { if (PHIBB == SDB->BitTestCases[i].Default) {
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
false)); false));
PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
false)); false));
PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
back().ThisBB)); back().ThisBB));
} }
// One of "cases" BB. // One of "cases" BB.
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
j != ej; ++j) { j != ej; ++j) {
MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
if (cBB->succ_end() != if (cBB->succ_end() !=
std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
false)); false));
PHI->addOperand(MachineOperand::CreateMBB(cBB)); PHI->addOperand(MachineOperand::CreateMBB(cBB));
} }
} }
} }
} }
SDL->BitTestCases.clear(); SDB->BitTestCases.clear();
// If the JumpTable record is filled in, then we need to emit a jump table. // If the JumpTable record is filled in, then we need to emit a jump table.
// Updating the PHI nodes is tricky in this case, since we need to determine // Updating the PHI nodes is tricky in this case, since we need to determine
// whether the PHI is a successor of the range check MBB or the jump table MBB // whether the PHI is a successor of the range check MBB or the jump table MBB
for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
// Lower header first, if it wasn't already lowered // Lower header first, if it wasn't already lowered
if (!SDL->JTCases[i].first.Emitted) { if (!SDB->JTCases[i].first.Emitted) {
// Set the current basic block to the mbb we wish to insert the code into // Set the current basic block to the mbb we wish to insert the code into
BB = SDL->JTCases[i].first.HeaderBB; BB = SDB->JTCases[i].first.HeaderBB;
SDL->setCurrentBasicBlock(BB); SDB->setCurrentBasicBlock(BB);
// Emit the code // Emit the code
SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
CurDAG->setRoot(SDL->getRoot()); CurDAG->setRoot(SDB->getRoot());
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
SDL->clear(); SDB->clear();
} }
// Set the current basic block to the mbb we wish to insert the code into // Set the current basic block to the mbb we wish to insert the code into
BB = SDL->JTCases[i].second.MBB; BB = SDB->JTCases[i].second.MBB;
SDL->setCurrentBasicBlock(BB); SDB->setCurrentBasicBlock(BB);
// Emit the code // Emit the code
SDL->visitJumpTable(SDL->JTCases[i].second); SDB->visitJumpTable(SDB->JTCases[i].second);
CurDAG->setRoot(SDL->getRoot()); CurDAG->setRoot(SDB->getRoot());
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
SDL->clear(); SDB->clear();
// Update PHI Nodes // Update PHI Nodes
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
MachineBasicBlock *PHIBB = PHI->getParent(); MachineBasicBlock *PHIBB = PHI->getParent();
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
// "default" BB. We can go there only from header BB. // "default" BB. We can go there only from header BB.
if (PHIBB == SDL->JTCases[i].second.Default) { if (PHIBB == SDB->JTCases[i].second.Default) {
PHI->addOperand PHI->addOperand
(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false)); (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
PHI->addOperand PHI->addOperand
(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
} }
// JT BB. Just iterate over successors here // JT BB. Just iterate over successors here
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
PHI->addOperand PHI->addOperand
(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false)); (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
PHI->addOperand(MachineOperand::CreateMBB(BB)); PHI->addOperand(MachineOperand::CreateMBB(BB));
} }
} }
} }
SDL->JTCases.clear(); SDB->JTCases.clear();
// If the switch block involved a branch to one of the actual successors, we // If the switch block involved a branch to one of the actual successors, we
// need to update PHI nodes in that block. // need to update PHI nodes in that block.
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
if (BB->isSuccessor(PHI->getParent())) { if (BB->isSuccessor(PHI->getParent())) {
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
false)); false));
PHI->addOperand(MachineOperand::CreateMBB(BB)); PHI->addOperand(MachineOperand::CreateMBB(BB));
} }
@ -1007,36 +1007,36 @@ SelectionDAGISel::FinishBasicBlock() {
// If we generated any switch lowering information, build and codegen any // If we generated any switch lowering information, build and codegen any
// additional DAGs necessary. // additional DAGs necessary.
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
// Set the current basic block to the mbb we wish to insert the code into // Set the current basic block to the mbb we wish to insert the code into
MachineBasicBlock *ThisBB = BB = SDL->SwitchCases[i].ThisBB; MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
SDL->setCurrentBasicBlock(BB); SDB->setCurrentBasicBlock(BB);
// Emit the code // Emit the code
SDL->visitSwitchCase(SDL->SwitchCases[i]); SDB->visitSwitchCase(SDB->SwitchCases[i]);
CurDAG->setRoot(SDL->getRoot()); CurDAG->setRoot(SDB->getRoot());
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
// Handle any PHI nodes in successors of this chunk, as if we were coming // Handle any PHI nodes in successors of this chunk, as if we were coming
// from the original BB before switch expansion. Note that PHI nodes can // from the original BB before switch expansion. Note that PHI nodes can
// occur multiple times in PHINodesToUpdate. We have to be very careful to // occur multiple times in PHINodesToUpdate. We have to be very careful to
// handle them the right number of times. // handle them the right number of times.
while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
// If new BB's are created during scheduling, the edges may have been // If new BB's are created during scheduling, the edges may have been
// updated. That is, the edge from ThisBB to BB may have been split and // updated. That is, the edge from ThisBB to BB may have been split and
// BB's predecessor is now another block. // BB's predecessor is now another block.
DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
SDL->EdgeMapping.find(BB); SDB->EdgeMapping.find(BB);
if (EI != SDL->EdgeMapping.end()) if (EI != SDB->EdgeMapping.end())
ThisBB = EI->second; ThisBB = EI->second;
for (MachineBasicBlock::iterator Phi = BB->begin(); for (MachineBasicBlock::iterator Phi = BB->begin();
Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
// This value for this PHI node is recorded in PHINodesToUpdate, get it. // This value for this PHI node is recorded in PHINodesToUpdate, get it.
for (unsigned pn = 0; ; ++pn) { for (unsigned pn = 0; ; ++pn) {
assert(pn != SDL->PHINodesToUpdate.size() && assert(pn != SDB->PHINodesToUpdate.size() &&
"Didn't find PHI entry!"); "Didn't find PHI entry!");
if (SDL->PHINodesToUpdate[pn].first == Phi) { if (SDB->PHINodesToUpdate[pn].first == Phi) {
Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. Phi->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pn].
second, false)); second, false));
Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
break; break;
@ -1045,19 +1045,19 @@ SelectionDAGISel::FinishBasicBlock() {
} }
// Don't process RHS if same block as LHS. // Don't process RHS if same block as LHS.
if (BB == SDL->SwitchCases[i].FalseBB) if (BB == SDB->SwitchCases[i].FalseBB)
SDL->SwitchCases[i].FalseBB = 0; SDB->SwitchCases[i].FalseBB = 0;
// If we haven't handled the RHS, do so now. Otherwise, we're done. // If we haven't handled the RHS, do so now. Otherwise, we're done.
SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
SDL->SwitchCases[i].FalseBB = 0; SDB->SwitchCases[i].FalseBB = 0;
} }
assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
SDL->clear(); SDB->clear();
} }
SDL->SwitchCases.clear(); SDB->SwitchCases.clear();
SDL->PHINodesToUpdate.clear(); SDB->PHINodesToUpdate.clear();
} }