6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-08 18:30:04 +00:00
Code Issues Projects Releases Wiki Activity

Use "a" instead of "a0" in DataLayout.

Browse Source 
It means exactly the same and is just a bit shorter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2013-12-12 17:21:51 +00:00
parent 35e19348d9
commit 2053a06bd5
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/LangRef.rst
View File

@ -1147,7 +1147,7 @@ specifications are given in this list:
- ``f128:128:128`` - quad is 128-bit aligned
- ``v64:64:64`` - 64-bit vector is 64-bit aligned
- ``v128:128:128`` - 128-bit vector is 128-bit aligned
- ``a0:0:64`` - aggregates are 64-bit aligned
- ``a:0:64`` - aggregates are 64-bit aligned
When LLVM is determining the alignment for a given type, it uses the
following rules:

2
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -73,7 +73,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
DL("e-p:32:32:32-"
"i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
"f64:64:64-f32:32:32-a0:0-n32") ,
"f64:64:64-f32:32:32-a:0-n32") ,
Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget),

2
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -31,7 +31,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
// so that we can refer to it using LARL. We don't have any special
// requirements for stack variables though.
DL("E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
"-f32:32-f64:64-f128:64-a0:8:16-n32:64"),
"-f32:32-f64:64-f128:64-a:8:16-n32:64"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(*this, Subtarget) {
initAsmInfo();

2
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -27,7 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
DL("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
DL("e-p:32:32:32-a:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),
InstrInfo(),
FrameLowering(Subtarget),