diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
index 42f6b063700..90656e47f85 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
@@ -188,8 +188,8 @@ public:
 ///
 class ScheduleDAGSimple : public ScheduleDAG {
 private:
-  SchedHeuristics Heuristic;            // Scheduling heuristic
-
+  bool NoSched;                         // Just do a BFS schedule, nothing fancy
+  bool NoItins;                         // Don't use itineraries?
   ResourceTally<unsigned> Tally;        // Resource usage tally
   unsigned NSlots;                      // Total latency
   static const unsigned NotFound = ~0U; // Search marker
@@ -204,9 +204,9 @@ private:
 public:
 
   // Ctor.
-  ScheduleDAGSimple(SchedHeuristics hstc, SelectionDAG &dag,
+  ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
                     MachineBasicBlock *bb, const TargetMachine &tm)
-    : ScheduleDAG(dag, bb, tm), Heuristic(hstc), Tally(), NSlots(0),
+    : ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
     NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
     assert(&TII && "Target doesn't provide instr info?");
     assert(&MRI && "Target doesn't provide register info?");
@@ -591,7 +591,7 @@ void ScheduleDAGSimple::GatherSchedulingInfo() {
     SDNode *Node = NI->Node;
     
     // If there are itineraries and it is a machine instruction
-    if (InstrItins.isEmpty() || Heuristic == simpleNoItinScheduling) {
+    if (InstrItins.isEmpty() || NoItins) {
       // If machine opcode
       if (Node->isTargetOpcode()) {
         // Get return type to guess which processing unit 
@@ -859,7 +859,7 @@ void ScheduleDAGSimple::Schedule() {
   IdentifyGroups();
   
   // Test to see if scheduling should occur
-  bool ShouldSchedule = NodeCount > 3 && Heuristic != noScheduling;
+  bool ShouldSchedule = NodeCount > 3 && !NoSched;
   // Don't waste time if is only entry and return
   if (ShouldSchedule) {
     // Get latency and resource requirements
@@ -899,8 +899,13 @@ void ScheduleDAGSimple::Schedule() {
 
 /// createSimpleDAGScheduler - This creates a simple two pass instruction
 /// scheduler.
-llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SchedHeuristics Heuristic,
+llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(bool NoItins,
                                                   SelectionDAG &DAG,
                                                   MachineBasicBlock *BB) {
-  return new ScheduleDAGSimple(Heuristic, DAG, BB,  DAG.getTarget());
+  return new ScheduleDAGSimple(false, NoItins, DAG, BB, DAG.getTarget());
+}
+
+llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG &DAG,
+                                                MachineBasicBlock *BB) {
+  return new ScheduleDAGSimple(true, false, DAG, BB,  DAG.getTarget());
 }
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 26a87179991..fc8e560aaf4 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -57,6 +57,16 @@ static const bool ViewISelDAGs = 0;
 static const bool ViewSchedDAGs = 0;
 #endif
 
+// Scheduling heuristics
+enum SchedHeuristics {
+  defaultScheduling,      // Let the target specify its preference.
+  noScheduling,           // No scheduling, emit breadth first sequence.
+  simpleScheduling,       // Two pass, min. critical path, max. utilization.
+  simpleNoItinScheduling, // Same as above exact using generic latency.
+  listSchedulingBURR,     // Bottom up reg reduction list scheduling.
+  listSchedulingTD        // Top-down list scheduler.
+};
+
 namespace {
   cl::opt<SchedHeuristics>
   ISHeuristic(
@@ -2444,9 +2454,13 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
       SL = createBURRListDAGScheduler(DAG, BB);
     break;
   case noScheduling:
+    SL = createBFS_DAGScheduler(DAG, BB);
+    break;
   case simpleScheduling:
+    SL = createSimpleDAGScheduler(false, DAG, BB);
+    break;
   case simpleNoItinScheduling:
-    SL = createSimpleDAGScheduler(ISHeuristic, DAG, BB);
+    SL = createSimpleDAGScheduler(true, DAG, BB);
     break;
   case listSchedulingBURR:
     SL = createBURRListDAGScheduler(DAG, BB);