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Add support for undef

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-18 23:10:57 +00:00
parent 311f8c21d0
commit 20ad53ffd7
4 changed files with 24 additions and 12 deletions
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8
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -111,7 +111,13 @@ def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
[(callseq_end imm:$amt)]>;
def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>;
def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
"!IMPLICIT_DEF $dst",
[(set IntRegs:$dst, (undef))]>;
def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set FPRegs:$dst, (undef))]>;
def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set DFPRegs:$dst, (undef))]>;
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpMOVD", []>; // pseudo 64-bit double move

10
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -243,9 +243,9 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
abort();
}
} else if (isa<UndefValue>(C)) {
BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R);
if (getClassB (C->getType ()) == cLong)
BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R+1);
return;
}
@ -341,15 +341,15 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
case cShort:
case cInt:
case cFloat:
BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
break;
case cDouble:
case cLong:
// Double and Long use register pairs.
BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
++ArgNo;
if (ArgNo < 6)
BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
break;
default:
assert (0 && "type not handled");

10
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -243,9 +243,9 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
abort();
}
} else if (isa<UndefValue>(C)) {
BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R);
if (getClassB (C->getType ()) == cLong)
BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R+1);
return;
}
@ -341,15 +341,15 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
case cShort:
case cInt:
case cFloat:
BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
break;
case cDouble:
case cLong:
// Double and Long use register pairs.
BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
++ArgNo;
if (ArgNo < 6)
BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
break;
default:
assert (0 && "type not handled");

8
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -111,7 +111,13 @@ def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
[(callseq_end imm:$amt)]>;
def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>;
def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
"!IMPLICIT_DEF $dst",
[(set IntRegs:$dst, (undef))]>;
def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set FPRegs:$dst, (undef))]>;
def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set DFPRegs:$dst, (undef))]>;
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpMOVD", []>; // pseudo 64-bit double move