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[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191154 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2013-09-21 23:51:08 +00:00
parent 1ce1525ed4
commit 20b5879e0e
2 changed files with 23 additions and 6 deletions
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12
lib/Target/Sparc/SparcISelLowering.cpp
View File

@@ -2160,12 +2160,12 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
return RetAddr; return RetAddr;
} }
static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG) static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
{ {
SDLoc dl(Op); SDLoc dl(Op);
assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
assert(Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS); assert(opcode == ISD::FNEG || opcode == ISD::FABS);
// Lower fneg/fabs on f64 to fneg/fabs on f32. // Lower fneg/fabs on f64 to fneg/fabs on f32.
// fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
@@ -2177,7 +2177,7 @@ static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG)
SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
SrcReg64); SrcReg64);
Hi32 = DAG.getNode(Op.getOpcode(), dl, MVT::f32, Hi32); Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, MVT::f64), 0); dl, MVT::f64), 0);
@@ -2280,7 +2280,7 @@ static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
const SparcTargetLowering &TLI, const SparcTargetLowering &TLI,
bool is64Bit) { bool is64Bit) {
if (Op.getValueType() == MVT::f64) if (Op.getValueType() == MVT::f64)
return LowerF64Op(Op, DAG); return LowerF64Op(Op, DAG, ISD::FNEG);
if (Op.getValueType() == MVT::f128) if (Op.getValueType() == MVT::f128)
return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1); return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
return Op; return Op;
@@ -2288,7 +2288,7 @@ static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
if (Op.getValueType() == MVT::f64) if (Op.getValueType() == MVT::f64)
return LowerF64Op(Op, DAG); return LowerF64Op(Op, DAG, ISD::FABS);
if (Op.getValueType() != MVT::f128) if (Op.getValueType() != MVT::f128)
return Op; return Op;
@@ -2304,7 +2304,7 @@ static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
if (isV9) if (isV9)
Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
else else
Hi64 = LowerF64Op(Op, DAG); Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, MVT::f128), 0); dl, MVT::f128), 0);

17
test/CodeGen/SPARC/fp128.ll
View File

@@ -96,3 +96,20 @@ entry:
"7": ; preds = %entry "7": ; preds = %entry
ret i32 1 ret i32 1
} }
; HARD-LABEL: f128_abs
; HARD: fabss
; SOFT-LABEL: f128_abs
; SOFT: fabss
define void @f128_abs(fp128* noalias sret %scalar.result, fp128* byval %a) {
entry:
%0 = load fp128* %a, align 8
%1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
store fp128 %1, fp128* %scalar.result, align 8
ret void
}
declare fp128 @llvm.fabs.f128(fp128) nounwind readonly