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Define proper subreg sets for arm - this should fix bunch of subtle problems
with subreg - superreg mapping and also fix PR4965. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81657 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
d11c4de5ce
commit
20c35ec427
@ -18,8 +18,8 @@ class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
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let SubRegs = subregs;
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}
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class ARMFReg<bits<5> num, string n> : Register<n> {
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field bits<5> Num;
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class ARMFReg<bits<6> num, string n> : Register<n> {
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field bits<6> Num;
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let Namespace = "ARM";
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}
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@ -58,6 +58,7 @@ def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
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def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
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def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
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def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
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def SDummy : ARMFReg<63, "sINVALID">;
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// Aliases of the F* registers used to hold 64-bit fp values (doubles)
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def D0 : ARMReg< 0, "d0", [S0, S1]>;
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@ -253,6 +254,17 @@ def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
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S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
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// Subset of SPR which can be used as a source of NEON scalars for 16-bit
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// operations
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def SPR_8 : RegisterClass<"ARM", [f32], 32,
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[S0, S1, S2, S3, S4, S5, S6, S7,
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S8, S9, S10, S11, S12, S13, S14, S15]>;
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// Dummy f32 regclass to represent impossible subreg indices.
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def SPR_INVALID : RegisterClass<"ARM", [f32], 32, [SDummy]> {
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let CopyCost = -1;
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}
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// Scalar double precision floating point / generic 64-bit vector register
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// class.
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// ARM requires only word alignment for double. It's more performant if it
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@ -262,7 +274,7 @@ def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
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D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31]> {
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let SubRegClassList = [SPR, SPR];
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let SubRegClassList = [SPR_INVALID, SPR_INVALID];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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@ -317,14 +329,22 @@ def DPR_VFP2 : RegisterClass<"ARM", [f64, v2i32, v2f32], 64,
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// operations
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def DPR_8 : RegisterClass<"ARM", [f64, v4i16, v2f32], 64,
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[D0, D1, D2, D3, D4, D5, D6, D7]> {
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let SubRegClassList = [SPR, SPR];
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let SubRegClassList = [SPR_8, SPR_8];
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}
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// Generic 128-bit vector register class.
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def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
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let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
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let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
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DPR, DPR];
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}
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// Subset of QPR that have 32-bit SPR subregs.
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def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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128,
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
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let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
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}
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// Subset of QPR that have 32-bit SPR subregs.
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61
test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
Normal file
61
test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
Normal file
@ -0,0 +1,61 @@
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; RUN: llc -mattr=+neon < %s
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; PR4965
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "armv7-eabi"
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%struct.fr = type { [6 x %struct.pl] }
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%struct.obb = type { %"struct.m4", %"struct.p3" }
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%struct.pl = type { %"struct.p3" }
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%"struct.m4" = type { %"struct.p3", %"struct.p3", %"struct.p3", %"struct.p3" }
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%"struct.p3" = type { <4 x float> }
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declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind {
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entry:
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%val.i.i = load <4 x float>* undef ; <<4 x float>> [#uses=1]
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%val2.i.i = load <4 x float>* null ; <<4 x float>> [#uses=1]
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%elt3.i.i = getelementptr inbounds %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
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%val4.i.i = load <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1]
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%0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
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%1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]
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br label %bb33
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bb: ; preds = %bb33
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%2 = fmul <4 x float> %val.i.i, undef ; <<4 x float>> [#uses=1]
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%3 = fmul <4 x float> %val2.i.i, undef ; <<4 x float>> [#uses=1]
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%4 = fadd <4 x float> %3, %2 ; <<4 x float>> [#uses=1]
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%5 = fmul <4 x float> %val4.i.i, undef ; <<4 x float>> [#uses=1]
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%6 = fadd <4 x float> %5, %4 ; <<4 x float>> [#uses=1]
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%7 = bitcast <4 x float> %6 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%8 = and <4 x i32> %7, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]
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%9 = or <4 x i32> %8, undef ; <<4 x i32>> [#uses=1]
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%10 = bitcast <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]
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%11 = shufflevector <4 x float> %10, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
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%12 = shufflevector <2 x float> %11, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%13 = fmul <4 x float> undef, %12 ; <<4 x float>> [#uses=1]
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%14 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=1]
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%15 = fadd <4 x float> %14, %13 ; <<4 x float>> [#uses=1]
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%16 = fadd <4 x float> undef, %15 ; <<4 x float>> [#uses=1]
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%17 = fadd <4 x float> %1, %16 ; <<4 x float>> [#uses=1]
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%18 = fmul <4 x float> zeroinitializer, %17 ; <<4 x float>> [#uses=1]
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%19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=2]
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%20 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
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%21 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
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%22 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %20, <2 x float> %21) nounwind ; <<2 x float>> [#uses=2]
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%23 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %22, <2 x float> %22) nounwind ; <<2 x float>> [#uses=2]
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%24 = shufflevector <2 x float> %23, <2 x float> %23, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%25 = fadd <4 x float> %24, zeroinitializer ; <<4 x float>> [#uses=1]
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%tmp46 = extractelement <4 x float> %25, i32 0 ; <float> [#uses=1]
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%26 = fcmp olt float %tmp46, 0.000000e+00 ; <i1> [#uses=1]
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br i1 %26, label %bb41, label %bb33
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bb33: ; preds = %bb, %entry
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br i1 undef, label %bb34, label %bb
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bb34: ; preds = %bb33
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ret i8 undef
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bb41: ; preds = %bb
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ret i8 1
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}
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