6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-06 09:44:39 +00:00
Code Issues Projects Releases Wiki Activity

[X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228283 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-02-05 08:51:06 +00:00
parent b8fa51de42
commit 20d15157e4
3 changed files with 27 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/X86/X86InstrInfo.td
View File

@ -2409,6 +2409,16 @@ let Predicates = [HasTBM] in {
(TZMSK64rr GR64:$src)>;
} // HasTBM
//===----------------------------------------------------------------------===//
// Memory Instructions
//
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", []>, PD;
def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
//===----------------------------------------------------------------------===//
// Subsystems.
//===----------------------------------------------------------------------===//

4
lib/Target/X86/X86InstrSSE.td
View File

@ -3975,7 +3975,7 @@ let SchedRW = [WriteLoad] in {
// Flush cache
def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
}
let SchedRW = [WriteNop] in {
@ -3990,7 +3990,7 @@ let SchedRW = [WriteFence] in {
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
"sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
TB, Requires<[HasSSE1]>;
PS, Requires<[HasSSE1]>;
def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
"lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
TB, Requires<[HasSSE2]>;

17
lib/Target/X86/X86InstrSystem.td
View File

@ -492,9 +492,22 @@ let Uses = [RDX, RAX] in {
def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
"xrstor64\t$dst", []>, TB, Requires<[In64BitMode]>;
def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
"xsaveopt\t$dst", []>, TB;
"xsaveopt\t$dst", []>, PS;
def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
"xsaveopt64\t$dst", []>, TB, Requires<[In64BitMode]>;
"xsaveopt64\t$dst", []>, PS, Requires<[In64BitMode]>;
def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
"xrstors\t$dst", []>, TB;
def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
"xrstors64\t$dst", []>, TB, Requires<[In64BitMode]>;
def XSAVEC : I<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
"xsavec\t$dst", []>, TB;
def XSAVEC64 : RI<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
"xsavec64\t$dst", []>, TB, Requires<[In64BitMode]>;
def XSAVES : I<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
"xsaves\t$dst", []>, TB;
def XSAVES64 : RI<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
"xsaves64\t$dst", []>, TB, Requires<[In64BitMode]>;
}
} // SchedRW