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[X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228283 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2409,6 +2409,16 @@ let Predicates = [HasTBM] in {
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(TZMSK64rr GR64:$src)>;
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} // HasTBM
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//===----------------------------------------------------------------------===//
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// Memory Instructions
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//
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def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflushopt\t$src", []>, PD;
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def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
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def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
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//===----------------------------------------------------------------------===//
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// Subsystems.
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//===----------------------------------------------------------------------===//
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@ -3975,7 +3975,7 @@ let SchedRW = [WriteLoad] in {
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
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IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
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IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
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}
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let SchedRW = [WriteNop] in {
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@ -3990,7 +3990,7 @@ let SchedRW = [WriteFence] in {
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// Load, store, and memory fence
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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"sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
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TB, Requires<[HasSSE1]>;
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PS, Requires<[HasSSE1]>;
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def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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"lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
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TB, Requires<[HasSSE2]>;
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@ -492,9 +492,22 @@ let Uses = [RDX, RAX] in {
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def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
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"xrstor64\t$dst", []>, TB, Requires<[In64BitMode]>;
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def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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"xsaveopt\t$dst", []>, TB;
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"xsaveopt\t$dst", []>, PS;
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def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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"xsaveopt64\t$dst", []>, TB, Requires<[In64BitMode]>;
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"xsaveopt64\t$dst", []>, PS, Requires<[In64BitMode]>;
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def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
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"xrstors\t$dst", []>, TB;
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def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
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"xrstors64\t$dst", []>, TB, Requires<[In64BitMode]>;
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def XSAVEC : I<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
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"xsavec\t$dst", []>, TB;
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def XSAVEC64 : RI<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
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"xsavec64\t$dst", []>, TB, Requires<[In64BitMode]>;
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def XSAVES : I<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
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"xsaves\t$dst", []>, TB;
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def XSAVES64 : RI<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
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"xsaves64\t$dst", []>, TB, Requires<[In64BitMode]>;
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}
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} // SchedRW
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