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Enable on-demand fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -161,7 +161,10 @@ unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
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}
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}
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} else if (const Operator *Op = dyn_cast<Operator>(V)) {
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if (!SelectOperator(Op, Op->getOpcode())) return 0;
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if (!SelectOperator(Op, Op->getOpcode()))
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if (!isa<Instruction>(Op) ||
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!TargetSelectInstruction(cast<Instruction>(Op)))
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return 0;
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Reg = lookUpRegForValue(Op);
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} else if (isa<UndefValue>(V)) {
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Reg = createResultReg(TLI.getRegClassFor(VT));
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@ -709,6 +709,12 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
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FastIS->startNewBlock(BB);
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// Do FastISel on as many instructions as possible.
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for (; BI != End; ++BI) {
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// Defer instructions with no side effects; they'll be emitted
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// on-demand later.
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if (BI->isSafeToSpeculativelyExecute() &&
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!FuncInfo->ValueMap.count(BI))
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continue;
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// Try to select the instruction with FastISel.
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if (FastIS->SelectInstruction(BI))
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continue;
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@ -935,7 +935,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
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CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
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const MachineInstr *SetMI = 0;
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unsigned Reg = lookUpRegForValue(EI);
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unsigned Reg = getRegForValue(EI);
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for (MachineBasicBlock::const_reverse_iterator
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RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
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@ -1,7 +1,8 @@
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; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax}
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; PR3242
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define i32 @foo(i32 %x) nounwind {
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define void @foo(i32 %x, i32* %p) nounwind {
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%y = ashr i32 %x, 50000
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ret i32 %y
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store i32 %y, i32* %p
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ret void
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}
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