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AArch64: remove barriers from AArch64 atomic operations.
I've managed to convince myself that AArch64's acquire/release instructions are sufficient to guarantee C++11's required semantics, even in the sequentially-consistent case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
724a7b145d
commit
211ffd242d
@ -88,6 +88,8 @@ public:
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bool SelectTSTBOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth);
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SDNode *SelectAtomic(SDNode *N, unsigned Op8, unsigned Op16, unsigned Op32, unsigned Op64);
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SDNode *TrySelectToMoveImm(SDNode *N);
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SDNode *LowerToFPLitPool(SDNode *Node);
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SDNode *SelectToLitPool(SDNode *N);
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@ -318,6 +320,38 @@ AArch64DAGToDAGISel::SelectTSTBOperand(SDValue N, SDValue &FixedPos,
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return true;
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}
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SDNode *AArch64DAGToDAGISel::SelectAtomic(SDNode *Node, unsigned Op8,
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unsigned Op16,unsigned Op32,
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unsigned Op64) {
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// Mostly direct translation to the given operations, except that we preserve
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// the AtomicOrdering for use later on.
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AtomicSDNode *AN = cast<AtomicSDNode>(Node);
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EVT VT = AN->getMemoryVT();
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unsigned Op;
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if (VT == MVT::i8)
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Op = Op8;
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else if (VT == MVT::i16)
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Op = Op16;
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else if (VT == MVT::i32)
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Op = Op32;
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else if (VT == MVT::i64)
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Op = Op64;
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else
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llvm_unreachable("Unexpected atomic operation");
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 1; i < AN->getNumOperands(); ++i)
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Ops.push_back(AN->getOperand(i));
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Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
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Ops.push_back(AN->getOperand(0)); // Chain moves to the end
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return CurDAG->SelectNodeTo(Node, Op,
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AN->getValueType(0), MVT::Other,
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&Ops[0], Ops.size());
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}
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SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
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// Dump information about the Node being selected
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DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << "\n");
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@ -328,6 +362,78 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
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}
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switch (Node->getOpcode()) {
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case ISD::ATOMIC_LOAD_ADD:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_ADD_I8,
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AArch64::ATOMIC_LOAD_ADD_I16,
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AArch64::ATOMIC_LOAD_ADD_I32,
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AArch64::ATOMIC_LOAD_ADD_I64);
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case ISD::ATOMIC_LOAD_SUB:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_SUB_I8,
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AArch64::ATOMIC_LOAD_SUB_I16,
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AArch64::ATOMIC_LOAD_SUB_I32,
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AArch64::ATOMIC_LOAD_SUB_I64);
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case ISD::ATOMIC_LOAD_AND:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_AND_I8,
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AArch64::ATOMIC_LOAD_AND_I16,
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AArch64::ATOMIC_LOAD_AND_I32,
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AArch64::ATOMIC_LOAD_AND_I64);
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case ISD::ATOMIC_LOAD_OR:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_OR_I8,
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AArch64::ATOMIC_LOAD_OR_I16,
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AArch64::ATOMIC_LOAD_OR_I32,
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AArch64::ATOMIC_LOAD_OR_I64);
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case ISD::ATOMIC_LOAD_XOR:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_XOR_I8,
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AArch64::ATOMIC_LOAD_XOR_I16,
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AArch64::ATOMIC_LOAD_XOR_I32,
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AArch64::ATOMIC_LOAD_XOR_I64);
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case ISD::ATOMIC_LOAD_NAND:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_NAND_I8,
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AArch64::ATOMIC_LOAD_NAND_I16,
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AArch64::ATOMIC_LOAD_NAND_I32,
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AArch64::ATOMIC_LOAD_NAND_I64);
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case ISD::ATOMIC_LOAD_MIN:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_MIN_I8,
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AArch64::ATOMIC_LOAD_MIN_I16,
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AArch64::ATOMIC_LOAD_MIN_I32,
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AArch64::ATOMIC_LOAD_MIN_I64);
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case ISD::ATOMIC_LOAD_MAX:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_MAX_I8,
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AArch64::ATOMIC_LOAD_MAX_I16,
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AArch64::ATOMIC_LOAD_MAX_I32,
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AArch64::ATOMIC_LOAD_MAX_I64);
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case ISD::ATOMIC_LOAD_UMIN:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_UMIN_I8,
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AArch64::ATOMIC_LOAD_UMIN_I16,
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AArch64::ATOMIC_LOAD_UMIN_I32,
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AArch64::ATOMIC_LOAD_UMIN_I64);
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case ISD::ATOMIC_LOAD_UMAX:
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return SelectAtomic(Node,
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AArch64::ATOMIC_LOAD_UMAX_I8,
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AArch64::ATOMIC_LOAD_UMAX_I16,
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AArch64::ATOMIC_LOAD_UMAX_I32,
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AArch64::ATOMIC_LOAD_UMAX_I64);
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case ISD::ATOMIC_SWAP:
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return SelectAtomic(Node,
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AArch64::ATOMIC_SWAP_I8,
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AArch64::ATOMIC_SWAP_I16,
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AArch64::ATOMIC_SWAP_I32,
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AArch64::ATOMIC_SWAP_I64);
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case ISD::ATOMIC_CMP_SWAP:
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return SelectAtomic(Node,
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AArch64::ATOMIC_CMP_SWAP_I8,
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AArch64::ATOMIC_CMP_SWAP_I16,
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AArch64::ATOMIC_CMP_SWAP_I32,
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AArch64::ATOMIC_CMP_SWAP_I64);
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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EVT PtrTy = TLI.getPointerTy();
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@ -59,12 +59,9 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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computeRegisterProperties();
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// Some atomic operations can be folded into load-acquire or store-release
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// instructions on AArch64. It's marginally simpler to let LLVM expand
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// everything out to a barrier and then recombine the (few) barriers we can.
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setInsertFencesForAtomic(true);
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setTargetDAGCombine(ISD::ATOMIC_FENCE);
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setTargetDAGCombine(ISD::ATOMIC_STORE);
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// We have particularly efficient implementations of atomic fences if they can
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// be combined with nearby atomic loads and stores.
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setShouldFoldAtomicFences(true);
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// We combine OR nodes for bitfield and NEON BSL operations.
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setTargetDAGCombine(ISD::OR);
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@ -275,27 +272,34 @@ EVT AArch64TargetLowering::getSetCCResultType(EVT VT) const {
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return VT.changeVectorElementTypeToInteger();
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}
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static void getExclusiveOperation(unsigned Size, unsigned &ldrOpc,
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unsigned &strOpc) {
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switch (Size) {
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default: llvm_unreachable("unsupported size for atomic binary op!");
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case 1:
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ldrOpc = AArch64::LDXR_byte;
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strOpc = AArch64::STXR_byte;
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break;
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case 2:
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ldrOpc = AArch64::LDXR_hword;
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strOpc = AArch64::STXR_hword;
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break;
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case 4:
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ldrOpc = AArch64::LDXR_word;
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strOpc = AArch64::STXR_word;
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break;
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case 8:
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ldrOpc = AArch64::LDXR_dword;
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strOpc = AArch64::STXR_dword;
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break;
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}
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static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
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unsigned &LdrOpc,
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unsigned &StrOpc) {
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static unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
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AArch64::LDXR_word, AArch64::LDXR_dword};
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static unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
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AArch64::LDAXR_word, AArch64::LDAXR_dword};
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static unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
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AArch64::STXR_word, AArch64::STXR_dword};
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static unsigned StoreRels[] = {AArch64::STLXR_byte, AArch64::STLXR_hword,
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AArch64::STLXR_word, AArch64::STLXR_dword};
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unsigned *LoadOps, *StoreOps;
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if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
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LoadOps = LoadAcqs;
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else
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LoadOps = LoadBares;
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if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
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StoreOps = StoreRels;
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else
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StoreOps = StoreBares;
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assert(isPowerOf2_32(Size) && Size <= 8 &&
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"unsupported size for atomic binary op!");
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LdrOpc = LoadOps[Log2_32(Size)];
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StrOpc = StoreOps[Log2_32(Size)];
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}
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MachineBasicBlock *
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@ -313,12 +317,13 @@ AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned incr = MI->getOperand(2).getReg();
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AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
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DebugLoc dl = MI->getDebugLoc();
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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unsigned ldrOpc, strOpc;
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getExclusiveOperation(Size, ldrOpc, strOpc);
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getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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@ -397,6 +402,8 @@ AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned incr = MI->getOperand(2).getReg();
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AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
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unsigned oldval = dest;
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DebugLoc dl = MI->getDebugLoc();
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@ -411,7 +418,7 @@ AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
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}
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unsigned ldrOpc, strOpc;
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getExclusiveOperation(Size, ldrOpc, strOpc);
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getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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@ -479,6 +486,7 @@ AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned oldval = MI->getOperand(2).getReg();
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unsigned newval = MI->getOperand(3).getReg();
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AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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@ -487,7 +495,7 @@ AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
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unsigned ldrOpc, strOpc;
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getExclusiveOperation(Size, ldrOpc, strOpc);
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getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
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MachineFunction *MF = BB->getParent();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -2377,78 +2385,6 @@ static SDValue PerformANDCombine(SDNode *N,
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DAG.getConstant(LSB + Width - 1, MVT::i64));
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}
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static SDValue PerformATOMIC_FENCECombine(SDNode *FenceNode,
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TargetLowering::DAGCombinerInfo &DCI) {
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// An atomic operation followed by an acquiring atomic fence can be reduced to
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// an acquiring load. The atomic operation provides a convenient pointer to
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// load from. If the original operation was a load anyway we can actually
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// combine the two operations into an acquiring load.
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SelectionDAG &DAG = DCI.DAG;
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SDValue AtomicOp = FenceNode->getOperand(0);
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AtomicSDNode *AtomicNode = dyn_cast<AtomicSDNode>(AtomicOp);
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// A fence on its own can't be optimised
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if (!AtomicNode)
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return SDValue();
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AtomicOrdering FenceOrder
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= static_cast<AtomicOrdering>(FenceNode->getConstantOperandVal(1));
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SynchronizationScope FenceScope
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= static_cast<SynchronizationScope>(FenceNode->getConstantOperandVal(2));
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if (FenceOrder != Acquire || FenceScope != AtomicNode->getSynchScope())
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return SDValue();
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// If the original operation was an ATOMIC_LOAD then we'll be replacing it, so
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// the chain we use should be its input, otherwise we'll put our store after
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// it so we use its output chain.
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SDValue Chain = AtomicNode->getOpcode() == ISD::ATOMIC_LOAD ?
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AtomicNode->getChain() : AtomicOp;
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// We have an acquire fence with a handy atomic operation nearby, we can
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// convert the fence into a load-acquire, discarding the result.
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DebugLoc DL = FenceNode->getDebugLoc();
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SDValue Op = DAG.getAtomic(ISD::ATOMIC_LOAD, DL, AtomicNode->getMemoryVT(),
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AtomicNode->getValueType(0),
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Chain, // Chain
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AtomicOp.getOperand(1), // Pointer
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AtomicNode->getMemOperand(), Acquire,
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FenceScope);
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if (AtomicNode->getOpcode() == ISD::ATOMIC_LOAD)
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DAG.ReplaceAllUsesWith(AtomicNode, Op.getNode());
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return Op.getValue(1);
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}
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static SDValue PerformATOMIC_STORECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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// A releasing atomic fence followed by an atomic store can be combined into a
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// single store operation.
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SelectionDAG &DAG = DCI.DAG;
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AtomicSDNode *AtomicNode = cast<AtomicSDNode>(N);
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SDValue FenceOp = AtomicNode->getOperand(0);
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if (FenceOp.getOpcode() != ISD::ATOMIC_FENCE)
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return SDValue();
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AtomicOrdering FenceOrder
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= static_cast<AtomicOrdering>(FenceOp->getConstantOperandVal(1));
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SynchronizationScope FenceScope
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= static_cast<SynchronizationScope>(FenceOp->getConstantOperandVal(2));
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if (FenceOrder != Release || FenceScope != AtomicNode->getSynchScope())
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return SDValue();
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DebugLoc DL = AtomicNode->getDebugLoc();
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return DAG.getAtomic(ISD::ATOMIC_STORE, DL, AtomicNode->getMemoryVT(),
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FenceOp.getOperand(0), // Chain
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AtomicNode->getOperand(1), // Pointer
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AtomicNode->getOperand(2), // Value
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AtomicNode->getMemOperand(), Release,
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FenceScope);
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}
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/// For a true bitfield insert, the bits getting into that contiguous mask
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/// should come from the low part of an existing value: they must be formed from
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/// a compatible SHL operation (unless they're already low). This function
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@ -2804,8 +2740,6 @@ AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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switch (N->getOpcode()) {
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default: break;
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case ISD::AND: return PerformANDCombine(N, DCI);
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case ISD::ATOMIC_FENCE: return PerformATOMIC_FENCECombine(N, DCI);
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case ISD::ATOMIC_STORE: return PerformATOMIC_STORECombine(N, DCI);
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case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
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case ISD::SRA: return PerformSRACombine(N, DCI);
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}
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@ -159,49 +159,55 @@ let Defs = [XSP], Uses = [XSP] in {
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// Atomic operation pseudo-instructions
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//===----------------------------------------------------------------------===//
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let usesCustomInserter = 1 in {
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multiclass AtomicSizes<string opname> {
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def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
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[(set i32:$dst, (!cast<SDNode>(opname # "_8") i64:$ptr, i32:$incr))]>;
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def _I16 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
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[(set i32:$dst, (!cast<SDNode>(opname # "_16") i64:$ptr, i32:$incr))]>;
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def _I32 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
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[(set i32:$dst, (!cast<SDNode>(opname # "_32") i64:$ptr, i32:$incr))]>;
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def _I64 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$incr),
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[(set i64:$dst, (!cast<SDNode>(opname # "_64") i64:$ptr, i64:$incr))]>;
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// These get selected from C++ code as a pretty much direct translation from the
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// generic DAG nodes. The one exception is the AtomicOrdering is added as an
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// operand so that the eventual lowering can make use of it and choose
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// acquire/release operations when required.
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let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
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multiclass AtomicSizes {
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def _I8 : PseudoInst<(outs GPR32:$dst),
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(ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
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def _I16 : PseudoInst<(outs GPR32:$dst),
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(ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
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def _I32 : PseudoInst<(outs GPR32:$dst),
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(ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
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def _I64 : PseudoInst<(outs GPR64:$dst),
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(ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
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}
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}
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defm ATOMIC_LOAD_ADD : AtomicSizes<"atomic_load_add">;
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defm ATOMIC_LOAD_SUB : AtomicSizes<"atomic_load_sub">;
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defm ATOMIC_LOAD_AND : AtomicSizes<"atomic_load_and">;
|
||||
defm ATOMIC_LOAD_OR : AtomicSizes<"atomic_load_or">;
|
||||
defm ATOMIC_LOAD_XOR : AtomicSizes<"atomic_load_xor">;
|
||||
defm ATOMIC_LOAD_NAND : AtomicSizes<"atomic_load_nand">;
|
||||
defm ATOMIC_SWAP : AtomicSizes<"atomic_swap">;
|
||||
defm ATOMIC_LOAD_ADD : AtomicSizes;
|
||||
defm ATOMIC_LOAD_SUB : AtomicSizes;
|
||||
defm ATOMIC_LOAD_AND : AtomicSizes;
|
||||
defm ATOMIC_LOAD_OR : AtomicSizes;
|
||||
defm ATOMIC_LOAD_XOR : AtomicSizes;
|
||||
defm ATOMIC_LOAD_NAND : AtomicSizes;
|
||||
defm ATOMIC_SWAP : AtomicSizes;
|
||||
let Defs = [NZCV] in {
|
||||
// These operations need a CMP to calculate the correct value
|
||||
defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">;
|
||||
defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">;
|
||||
defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">;
|
||||
defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">;
|
||||
defm ATOMIC_LOAD_MIN : AtomicSizes;
|
||||
defm ATOMIC_LOAD_MAX : AtomicSizes;
|
||||
defm ATOMIC_LOAD_UMIN : AtomicSizes;
|
||||
defm ATOMIC_LOAD_UMAX : AtomicSizes;
|
||||
}
|
||||
|
||||
let usesCustomInserter = 1, Defs = [NZCV] in {
|
||||
def ATOMIC_CMP_SWAP_I8
|
||||
: PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
|
||||
[(set i32:$dst, (atomic_cmp_swap_8 i64:$ptr, i32:$old, i32:$new))]>;
|
||||
def ATOMIC_CMP_SWAP_I16
|
||||
: PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
|
||||
[(set i32:$dst, (atomic_cmp_swap_16 i64:$ptr, i32:$old, i32:$new))]>;
|
||||
def ATOMIC_CMP_SWAP_I32
|
||||
: PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
|
||||
[(set i32:$dst, (atomic_cmp_swap_32 i64:$ptr, i32:$old, i32:$new))]>;
|
||||
def ATOMIC_CMP_SWAP_I64
|
||||
: PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$old, GPR64:$new),
|
||||
[(set i64:$dst, (atomic_cmp_swap_64 i64:$ptr, i64:$old, i64:$new))]>;
|
||||
class AtomicCmpSwap<RegisterClass GPRData>
|
||||
: PseudoInst<(outs GPRData:$dst),
|
||||
(ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
|
||||
i32imm:$ordering), []> {
|
||||
let usesCustomInserter = 1;
|
||||
let hasCtrlDep = 1;
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let Defs = [NZCV];
|
||||
}
|
||||
|
||||
def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
|
||||
def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
|
||||
def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
|
||||
def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Add-subtract (extended register) instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2579,7 +2585,8 @@ defm LDAR : A64I_LRex<"ldar", 0b101>;
|
||||
|
||||
class acquiring_load<PatFrag base>
|
||||
: PatFrag<(ops node:$ptr), (base node:$ptr), [{
|
||||
return cast<AtomicSDNode>(N)->getOrdering() == Acquire;
|
||||
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
|
||||
return Ordering == Acquire || Ordering == SequentiallyConsistent;
|
||||
}]>;
|
||||
|
||||
def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
|
||||
@ -2610,7 +2617,8 @@ class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
|
||||
|
||||
class releasing_store<PatFrag base>
|
||||
: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
|
||||
return cast<AtomicSDNode>(N)->getOrdering() == Release;
|
||||
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
|
||||
return Ordering == Release || Ordering == SequentiallyConsistent;
|
||||
}]>;
|
||||
|
||||
def atomic_store_release_8 : releasing_store<atomic_store_8>;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define i32 @foo(i32* %var, i1 %cond) {
|
||||
; CHECK: foo:
|
||||
@ -9,7 +9,9 @@ simple_ver:
|
||||
store i32 %newval, i32* %var
|
||||
br label %somewhere
|
||||
atomic_ver:
|
||||
%val = atomicrmw add i32* %var, i32 -1 seq_cst
|
||||
fence seq_cst
|
||||
%val = atomicrmw add i32* %var, i32 -1 monotonic
|
||||
fence seq_cst
|
||||
br label %somewhere
|
||||
; CHECK: dmb
|
||||
; CHECK: ldxr
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user