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Add llvm.x86.* intrinsics for Intel SHA Extensions
Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190864 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2881,3 +2881,24 @@ let TargetPrefix = "x86" in {
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
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[IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// SHA intrinsics
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let TargetPrefix = "x86" in {
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def int_x86_sha1rnds4 : GCCBuiltin<"__builtin_ia32_sha1rnds4">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_sha1nexte : GCCBuiltin<"__builtin_ia32_sha1nexte">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_sha1msg1 : GCCBuiltin<"__builtin_ia32_sha1msg1">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_sha1msg2 : GCCBuiltin<"__builtin_ia32_sha1msg2">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_sha256rnds2 : GCCBuiltin<"__builtin_ia32_sha256rnds2">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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def int_x86_sha256msg1 : GCCBuiltin<"__builtin_ia32_sha256msg1">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_sha256msg2 : GCCBuiltin<"__builtin_ia32_sha256msg2">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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}
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@ -7395,37 +7395,49 @@ let Constraints = "$src1 = $dst" in {
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// SHA-NI Instructions
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//===----------------------------------------------------------------------===//
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multiclass SHAI_binop<bits<8> Opc, string OpcodeStr> {
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multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
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bit UsesXMM0 = 0> {
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def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), []>, T8;
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
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let mayLoad = 1 in
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def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), []>, T8;
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
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(set VR128:$dst, (IntId VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
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}
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let Constraints = "$src1 = $dst", hasSideEffects = 0, Predicates = [HasSHA] in {
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let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
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def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, TA;
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let mayLoad = 1 in
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[(set VR128:$dst,
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(int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
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(i8 imm:$src3)))]>, TA;
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def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, TA;
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[(set VR128:$dst,
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(int_x86_sha1rnds4 VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)),
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(i8 imm:$src3)))]>, TA;
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defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte">;
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defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1">;
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defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2">;
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defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
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defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
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defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
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let Uses=[XMM0] in
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defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2">;
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defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
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defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1">;
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defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2">;
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defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
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defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
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}
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// Aliases with explicit %xmm0
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