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Make second source operand of LDRD pre/post explicit.

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Finish what r128736 started.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-04-05 18:40:13 +00:00
parent 7a8e6c5fb2
commit 215e4fdbf9
2 changed files with 28 additions and 8 deletions
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7
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1232,8 +1232,6 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
++OpIdx;
}
bool DualReg = HasDualReg(Opcode);
// Disassemble the dst/src operand.
if (OpIdx >= NumOps)
return false;
@ -1244,9 +1242,8 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRd(insn))));
++OpIdx;
// Fill in LDRD and STRD's second operand, but only if it's offset mode OR we
// have a pre-or-post-indexed store operation.
if (DualReg && (!isPrePost || isStore)) {
// Fill in LDRD and STRD's second operand Rt operand.
if (HasDualReg(Opcode)) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRd(insn) + 1)));
++OpIdx;