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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
MIPS DSP: add operands to make sure instruction strings are being matched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164849 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -74,7 +74,7 @@ entry:
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define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
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define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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entry:
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; CHECK: extp
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; CHECK: extp ${{[0-9]+}}
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%1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
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%1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
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ret i32 %1
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ret i32 %1
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@ -92,7 +92,7 @@ entry:
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define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
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define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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entry:
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; CHECK: extpdp
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; CHECK: extpdp ${{[0-9]+}}
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%1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
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%1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
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ret i32 %1
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ret i32 %1
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@ -262,7 +262,7 @@ declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
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define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {
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define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {
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entry:
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entry:
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; CHECK: shilo
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; CHECK: shilo $ac{{[0-9]}}
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%1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0)
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%1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0)
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ret i64 %1
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ret i64 %1
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@ -280,7 +280,7 @@ entry:
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define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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entry:
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entry:
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; CHECK: mthlip
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; CHECK: mthlip ${{[0-9]+}}
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%1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1)
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%1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1)
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ret i64 %1
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ret i64 %1
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@ -290,7 +290,7 @@ declare i64 @llvm.mips.mthlip(i64, i32) nounwind
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define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
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define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
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entry:
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entry:
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; CHECK: bposge32
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; CHECK: bposge32 $BB{{[0-9]+}}
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%0 = tail call i32 @llvm.mips.bposge32()
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%0 = tail call i32 @llvm.mips.bposge32()
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ret i32 %0
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ret i32 %0
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@ -300,7 +300,7 @@ declare i32 @llvm.mips.bposge32() nounwind readonly
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define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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entry:
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entry:
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; CHECK: madd
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; CHECK: madd $ac{{[0-9]}}
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%1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2)
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%1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2)
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ret i64 %1
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ret i64 %1
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@ -310,7 +310,7 @@ declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone
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define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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entry:
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entry:
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; CHECK: maddu
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; CHECK: maddu $ac{{[0-9]}}
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%1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2)
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%1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2)
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ret i64 %1
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ret i64 %1
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@ -320,7 +320,7 @@ declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone
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define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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entry:
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entry:
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; CHECK: msub
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; CHECK: msub $ac{{[0-9]}}
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%1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)
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%1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)
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ret i64 %1
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ret i64 %1
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@ -330,7 +330,7 @@ declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone
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define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
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entry:
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entry:
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; CHECK: msubu
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; CHECK: msubu $ac{{[0-9]}}
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%1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2)
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%1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2)
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ret i64 %1
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ret i64 %1
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@ -340,7 +340,7 @@ declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone
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define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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entry:
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; CHECK: mult
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; CHECK: mult $ac{{[0-9]}}
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%0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1)
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%0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1)
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ret i64 %0
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ret i64 %0
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@ -350,7 +350,7 @@ declare i64 @llvm.mips.mult(i32, i32) nounwind readnone
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define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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entry:
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; CHECK: multu
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; CHECK: multu $ac{{[0-9]}}
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%0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1)
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%0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1)
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ret i64 %0
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ret i64 %0
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@ -492,7 +492,7 @@ declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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entry:
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entry:
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; CHECK: addsc
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; CHECK: addsc ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1)
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%0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1)
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ret i32 %0
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ret i32 %0
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@ -502,7 +502,7 @@ declare i32 @llvm.mips.addsc(i32, i32) nounwind
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define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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entry:
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entry:
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; CHECK: addwc
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; CHECK: addwc ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1)
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%0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1)
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ret i32 %0
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ret i32 %0
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@ -512,7 +512,7 @@ declare i32 @llvm.mips.addwc(i32, i32) nounwind
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define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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entry:
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; CHECK: modsub
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; CHECK: modsub ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1)
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%0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1)
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ret i32 %0
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ret i32 %0
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@ -810,7 +810,7 @@ declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone
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define i32 @test__builtin_mips_rddsp1(i32 %i0) nounwind readonly {
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define i32 @test__builtin_mips_rddsp1(i32 %i0) nounwind readonly {
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entry:
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entry:
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; CHECK: rddsp
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; CHECK: rddsp ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.rddsp(i32 31)
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%0 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %0
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ret i32 %0
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@ -1191,7 +1191,7 @@ entry:
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define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone {
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define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone {
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entry:
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entry:
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; CHECK: bitrev
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; CHECK: bitrev ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.bitrev(i32 %a0)
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%0 = tail call i32 @llvm.mips.bitrev(i32 %a0)
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ret i32 %0
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ret i32 %0
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@ -1201,7 +1201,7 @@ declare i32 @llvm.mips.bitrev(i32) nounwind readnone
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define i32 @test__builtin_mips_lbux1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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define i32 @test__builtin_mips_lbux1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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entry:
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entry:
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; CHECK: lbux
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; CHECK: lbux ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.lbux(i8* %a0, i32 %a1)
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%0 = tail call i32 @llvm.mips.lbux(i8* %a0, i32 %a1)
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ret i32 %0
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ret i32 %0
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@ -1211,7 +1211,7 @@ declare i32 @llvm.mips.lbux(i8*, i32) nounwind readonly
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define i32 @test__builtin_mips_lhx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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define i32 @test__builtin_mips_lhx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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entry:
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entry:
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; CHECK: lhx
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; CHECK: lhx ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.lhx(i8* %a0, i32 %a1)
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%0 = tail call i32 @llvm.mips.lhx(i8* %a0, i32 %a1)
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ret i32 %0
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ret i32 %0
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@ -1221,7 +1221,7 @@ declare i32 @llvm.mips.lhx(i8*, i32) nounwind readonly
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define i32 @test__builtin_mips_lwx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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define i32 @test__builtin_mips_lwx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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entry:
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entry:
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; CHECK: lwx
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; CHECK: lwx ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.lwx(i8* %a0, i32 %a1)
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%0 = tail call i32 @llvm.mips.lwx(i8* %a0, i32 %a1)
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ret i32 %0
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ret i32 %0
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@ -1231,7 +1231,7 @@ declare i32 @llvm.mips.lwx(i8*, i32) nounwind readonly
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define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind {
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define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind {
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entry:
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entry:
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; CHECK: wrdsp
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; CHECK: wrdsp ${{[0-9]+}}
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tail call void @llvm.mips.wrdsp(i32 %a0, i32 31)
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tail call void @llvm.mips.wrdsp(i32 %a0, i32 31)
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%0 = tail call i32 @llvm.mips.rddsp(i32 31)
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%0 = tail call i32 @llvm.mips.rddsp(i32 31)
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@ -539,7 +539,7 @@ declare i32 @llvm.mips.subqh.r.w(i32, i32) nounwind readnone
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define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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entry:
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; CHECK: append
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; CHECK: append ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15)
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%0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15)
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ret i32 %0
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ret i32 %0
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@ -549,7 +549,7 @@ declare i32 @llvm.mips.append(i32, i32, i32) nounwind readnone
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define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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entry:
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; CHECK: balign
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; CHECK: balign ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1)
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%0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1)
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ret i32 %0
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ret i32 %0
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@ -559,7 +559,7 @@ declare i32 @llvm.mips.balign(i32, i32, i32) nounwind readnone
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define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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entry:
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; CHECK: prepend
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; CHECK: prepend ${{[0-9]+}}
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%0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15)
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%0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15)
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ret i32 %0
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ret i32 %0
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