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https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-25 05:22:04 +00:00
Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -355,43 +355,44 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const{
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (RC == PPC::GPRCRegisterClass) {
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if (SrcReg != PPC::LR) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
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.addReg(SrcReg, false, false, isKill),
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FrameIdx));
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
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NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
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.addReg(PPC::R11, false, false, isKill),
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FrameIdx));
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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if (SrcReg != PPC::LR8) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
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NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
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.addReg(PPC::X11, false, false, isKill), FrameIdx));
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else if (RC == PPC::F4RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else if (RC == PPC::CRRCRegisterClass) {
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if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
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(EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
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// FIXME (64-bit): Enable
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
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.addReg(SrcReg, false, false, isKill),
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FrameIdx));
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return true;
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@@ -399,18 +400,18 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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// FIXME: We use R0 here, because it isn't available for RA. We need to
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// store the CR in the low 4-bits of the saved value. First, issue a MFCR
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// to save all of the CRBits.
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NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
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NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
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// If the saved register wasn't CR0, shift the bits left so that they are
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// in CR0's slot.
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if (SrcReg != PPC::CR0) {
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unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
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// rlwinm r0, r0, ShiftBits, 0, 31.
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NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
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NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
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.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
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}
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
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.addReg(PPC::R0, false, false, isKill),
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FrameIdx));
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}
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@@ -446,9 +447,9 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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// STVX VAL, 0, R0
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
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FrameIdx, 0, 0));
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NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
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NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
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.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
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} else {
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assert(0 && "Unknown regclass!");
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@@ -490,6 +491,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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return;
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}
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DebugLoc DL = DebugLoc::getUnknownLoc();
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unsigned Opc = 0;
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if (RC == PPC::GPRCRegisterClass) {
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Opc = PPC::STW;
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@@ -505,7 +507,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
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.addReg(SrcReg, false, false, isKill);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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@@ -644,7 +646,8 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
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DebugLoc DL = DebugLoc::getUnknownLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isReg())
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