6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-09 11:25:55 +00:00
Code Issues Projects Releases Wiki Activity

Exploit the new identity composition in composeSubRegIndices().

Browse Source 
The static compose() function in RegisterCoalescer was doing the exact
same thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-11-01 01:15:43 +00:00
parent 5801ff93e3
commit 21caa9ef03
1 changed files with 8 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
lib/CodeGen/RegisterCoalescer.cpp
View File

@@ -198,12 +198,6 @@ INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
char RegisterCoalescer::ID = 0; char RegisterCoalescer::ID = 0;
static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
if (!a) return b;
if (!b) return a;
return tri.composeSubRegIndices(a, b);
}
static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
unsigned &Src, unsigned &Dst, unsigned &Src, unsigned &Dst,
unsigned &SrcSub, unsigned &DstSub) { unsigned &SrcSub, unsigned &DstSub) {
@@ -214,8 +208,8 @@ static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
SrcSub = MI->getOperand(1).getSubReg(); SrcSub = MI->getOperand(1).getSubReg();
} else if (MI->isSubregToReg()) { } else if (MI->isSubregToReg()) {
Dst = MI->getOperand(0).getReg(); Dst = MI->getOperand(0).getReg();
DstSub = compose(tri, MI->getOperand(0).getSubReg(), DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
MI->getOperand(3).getImm()); MI->getOperand(3).getImm());
Src = MI->getOperand(2).getReg(); Src = MI->getOperand(2).getReg();
SrcSub = MI->getOperand(2).getSubReg(); SrcSub = MI->getOperand(2).getSubReg();
} else } else
@@ -354,7 +348,8 @@ bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
if (DstReg != Dst) if (DstReg != Dst)
return false; return false;
// Registers match, do the subregisters line up? // Registers match, do the subregisters line up?
return compose(TRI, SrcIdx, SrcSub) == compose(TRI, DstIdx, DstSub); return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
TRI.composeSubRegIndices(DstIdx, DstSub);
} }
} }
@@ -1315,7 +1310,8 @@ unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef) {
for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) { for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef()) if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef())
continue; continue;
L |= TRI->getSubRegIndexLaneMask(compose(*TRI, SubIdx, MO->getSubReg())); L |= TRI->getSubRegIndexLaneMask(
TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
if (MO->readsReg()) if (MO->readsReg())
Redef = true; Redef = true;
} }
@@ -1647,8 +1643,8 @@ bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx,
continue; continue;
if (!MO->readsReg()) if (!MO->readsReg())
continue; continue;
if (Lanes & if (Lanes & TRI->getSubRegIndexLaneMask(
TRI->getSubRegIndexLaneMask(compose(*TRI, SubIdx, MO->getSubReg()))) TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
return true; return true;
} }
return false; return false;