mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
ARM prefix asmparser operand kind enums for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
2acf638216
commit
21ff17ce1b
@ -242,28 +242,28 @@ namespace {
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/// instruction.
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class ARMOperand : public MCParsedAsmOperand {
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enum KindTy {
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CondCode,
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CCOut,
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ITCondMask,
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CoprocNum,
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CoprocReg,
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Immediate,
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FPImmediate,
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MemBarrierOpt,
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Memory,
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PostIndexRegister,
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MSRMask,
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ProcIFlags,
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Register,
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RegisterList,
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DPRRegisterList,
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SPRRegisterList,
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ShiftedRegister,
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ShiftedImmediate,
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ShifterImmediate,
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RotateImmediate,
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BitfieldDescriptor,
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Token
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k_CondCode,
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k_CCOut,
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k_ITCondMask,
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k_CoprocNum,
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k_CoprocReg,
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k_Immediate,
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k_FPImmediate,
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k_MemBarrierOpt,
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k_Memory,
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k_PostIndexRegister,
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k_MSRMask,
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k_ProcIFlags,
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k_Register,
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k_RegisterList,
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k_DPRRegisterList,
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k_SPRRegisterList,
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k_ShiftedRegister,
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k_ShiftedImmediate,
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k_ShifterImmediate,
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k_RotateImmediate,
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k_BitfieldDescriptor,
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k_Token
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} Kind;
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SMLoc StartLoc, EndLoc;
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@ -361,62 +361,62 @@ public:
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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switch (Kind) {
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case CondCode:
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case k_CondCode:
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CC = o.CC;
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break;
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case ITCondMask:
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case k_ITCondMask:
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ITMask = o.ITMask;
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break;
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case Token:
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case k_Token:
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Tok = o.Tok;
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break;
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case CCOut:
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case Register:
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case k_CCOut:
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case k_Register:
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Reg = o.Reg;
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break;
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case RegisterList:
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case DPRRegisterList:
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case SPRRegisterList:
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case k_RegisterList:
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case k_DPRRegisterList:
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case k_SPRRegisterList:
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Registers = o.Registers;
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break;
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case CoprocNum:
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case CoprocReg:
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case k_CoprocNum:
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case k_CoprocReg:
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Cop = o.Cop;
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break;
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case Immediate:
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case k_Immediate:
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Imm = o.Imm;
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break;
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case FPImmediate:
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case k_FPImmediate:
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FPImm = o.FPImm;
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break;
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case MemBarrierOpt:
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case k_MemBarrierOpt:
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MBOpt = o.MBOpt;
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break;
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case Memory:
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case k_Memory:
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Mem = o.Mem;
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break;
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case PostIndexRegister:
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case k_PostIndexRegister:
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PostIdxReg = o.PostIdxReg;
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break;
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case MSRMask:
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case k_MSRMask:
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MMask = o.MMask;
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break;
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case ProcIFlags:
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case k_ProcIFlags:
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IFlags = o.IFlags;
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break;
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case ShifterImmediate:
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case k_ShifterImmediate:
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ShifterImm = o.ShifterImm;
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break;
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case ShiftedRegister:
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case k_ShiftedRegister:
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RegShiftedReg = o.RegShiftedReg;
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break;
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case ShiftedImmediate:
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case k_ShiftedImmediate:
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RegShiftedImm = o.RegShiftedImm;
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break;
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case RotateImmediate:
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case k_RotateImmediate:
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RotImm = o.RotImm;
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break;
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case BitfieldDescriptor:
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case k_BitfieldDescriptor:
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Bitfield = o.Bitfield;
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break;
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}
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@ -428,66 +428,66 @@ public:
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SMLoc getEndLoc() const { return EndLoc; }
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ARMCC::CondCodes getCondCode() const {
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assert(Kind == CondCode && "Invalid access!");
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assert(Kind == k_CondCode && "Invalid access!");
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return CC.Val;
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}
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unsigned getCoproc() const {
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assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
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assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
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return Cop.Val;
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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assert(Kind == k_Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert((Kind == Register || Kind == CCOut) && "Invalid access!");
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assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
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return Reg.RegNum;
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}
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const SmallVectorImpl<unsigned> &getRegList() const {
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assert((Kind == RegisterList || Kind == DPRRegisterList ||
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Kind == SPRRegisterList) && "Invalid access!");
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assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
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Kind == k_SPRRegisterList) && "Invalid access!");
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return Registers;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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assert(Kind == k_Immediate && "Invalid access!");
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return Imm.Val;
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}
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unsigned getFPImm() const {
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assert(Kind == FPImmediate && "Invalid access!");
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assert(Kind == k_FPImmediate && "Invalid access!");
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return FPImm.Val;
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}
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ARM_MB::MemBOpt getMemBarrierOpt() const {
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assert(Kind == MemBarrierOpt && "Invalid access!");
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assert(Kind == k_MemBarrierOpt && "Invalid access!");
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return MBOpt.Val;
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}
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ARM_PROC::IFlags getProcIFlags() const {
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assert(Kind == ProcIFlags && "Invalid access!");
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assert(Kind == k_ProcIFlags && "Invalid access!");
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return IFlags.Val;
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}
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unsigned getMSRMask() const {
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assert(Kind == MSRMask && "Invalid access!");
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assert(Kind == k_MSRMask && "Invalid access!");
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return MMask.Val;
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}
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bool isCoprocNum() const { return Kind == CoprocNum; }
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bool isCoprocReg() const { return Kind == CoprocReg; }
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bool isCondCode() const { return Kind == CondCode; }
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bool isCCOut() const { return Kind == CCOut; }
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bool isITMask() const { return Kind == ITCondMask; }
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bool isITCondCode() const { return Kind == CondCode; }
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bool isImm() const { return Kind == Immediate; }
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bool isFPImm() const { return Kind == FPImmediate; }
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bool isCoprocNum() const { return Kind == k_CoprocNum; }
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bool isCoprocReg() const { return Kind == k_CoprocReg; }
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bool isCondCode() const { return Kind == k_CondCode; }
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bool isCCOut() const { return Kind == k_CCOut; }
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bool isITMask() const { return Kind == k_ITCondMask; }
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bool isITCondCode() const { return Kind == k_CondCode; }
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bool isImm() const { return Kind == k_Immediate; }
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bool isFPImm() const { return Kind == k_FPImmediate; }
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bool isImm8s4() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -495,7 +495,7 @@ public:
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return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
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}
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bool isImm0_1020s4() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -503,7 +503,7 @@ public:
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return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
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}
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bool isImm0_508s4() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -511,7 +511,7 @@ public:
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return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
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}
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bool isImm0_255() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -519,7 +519,7 @@ public:
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return Value >= 0 && Value < 256;
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}
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bool isImm0_7() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -527,7 +527,7 @@ public:
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return Value >= 0 && Value < 8;
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}
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bool isImm0_15() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -535,7 +535,7 @@ public:
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return Value >= 0 && Value < 16;
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}
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bool isImm0_31() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -543,7 +543,7 @@ public:
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return Value >= 0 && Value < 32;
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}
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bool isImm1_16() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -551,7 +551,7 @@ public:
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return Value > 0 && Value < 17;
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}
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bool isImm1_32() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -559,7 +559,7 @@ public:
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return Value > 0 && Value < 33;
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}
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bool isImm0_65535() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -567,7 +567,7 @@ public:
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return Value >= 0 && Value < 65536;
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}
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bool isImm0_65535Expr() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// If it's not a constant expression, it'll generate a fixup and be
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@ -577,7 +577,7 @@ public:
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return Value >= 0 && Value < 65536;
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}
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bool isImm24bit() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -585,7 +585,7 @@ public:
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return Value >= 0 && Value <= 0xffffff;
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}
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bool isImmThumbSR() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -593,7 +593,7 @@ public:
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return Value > 0 && Value < 33;
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}
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bool isPKHLSLImm() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -601,7 +601,7 @@ public:
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return Value >= 0 && Value < 32;
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}
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bool isPKHASRImm() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -609,7 +609,7 @@ public:
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return Value > 0 && Value <= 32;
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}
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bool isARMSOImm() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -617,7 +617,7 @@ public:
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return ARM_AM::getSOImmVal(Value) != -1;
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}
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bool isT2SOImm() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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@ -625,37 +625,37 @@ public:
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return ARM_AM::getT2SOImmVal(Value) != -1;
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}
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bool isSetEndImm() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value == 1 || Value == 0;
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}
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bool isReg() const { return Kind == Register; }
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bool isRegList() const { return Kind == RegisterList; }
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bool isDPRRegList() const { return Kind == DPRRegisterList; }
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bool isSPRRegList() const { return Kind == SPRRegisterList; }
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bool isToken() const { return Kind == Token; }
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bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
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bool isMemory() const { return Kind == Memory; }
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bool isShifterImm() const { return Kind == ShifterImmediate; }
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bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
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bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
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bool isRotImm() const { return Kind == RotateImmediate; }
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bool isBitfield() const { return Kind == BitfieldDescriptor; }
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bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
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bool isReg() const { return Kind == k_Register; }
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bool isRegList() const { return Kind == k_RegisterList; }
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bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
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bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
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bool isToken() const { return Kind == k_Token; }
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bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
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bool isMemory() const { return Kind == k_Memory; }
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bool isShifterImm() const { return Kind == k_ShifterImmediate; }
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bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
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bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
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bool isRotImm() const { return Kind == k_RotateImmediate; }
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bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
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bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
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bool isPostIdxReg() const {
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return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
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return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
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}
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bool isMemNoOffset() const {
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if (Kind != Memory)
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if (Kind != k_Memory)
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return false;
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// No offset of any kind.
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return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
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}
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bool isAddrMode2() const {
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if (Kind != Memory)
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if (Kind != k_Memory)
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return false;
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// Check for register offset.
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if (Mem.OffsetRegNum) return true;
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@ -665,7 +665,7 @@ public:
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return Val > -4096 && Val < 4096;
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}
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bool isAM2OffsetImm() const {
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if (Kind != Immediate)
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if (Kind != k_Immediate)
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return false;
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// Immediate offset in range [-4095, 4095].
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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@ -674,7 +674,7 @@ public:
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return Val > -4096 && Val < 4096;
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}
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bool isAddrMode3() const {
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if (Kind != Memory)
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if (Kind != k_Memory)
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return false;
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// No shifts are legal for AM3.
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if (Mem.ShiftType != ARM_AM::no_shift) return false;
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@ -686,9 +686,9 @@ public:
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return Val > -256 && Val < 256;
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}
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bool isAM3Offset() const {
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if (Kind != Immediate && Kind != PostIndexRegister)
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if (Kind != k_Immediate && Kind != k_PostIndexRegister)
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return false;
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if (Kind == PostIndexRegister)
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if (Kind == k_PostIndexRegister)
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return PostIdxReg.ShiftTy == ARM_AM::no_shift;
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// Immediate offset in range [-255, 255].
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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@ -698,7 +698,7 @@ public:
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return (Val > -256 && Val < 256) || Val == INT32_MIN;
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}
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bool isAddrMode5() const {
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if (Kind != Memory)
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if (Kind != k_Memory)
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return false;
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// Check for register offset.
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if (Mem.OffsetRegNum) return false;
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@ -709,24 +709,24 @@ public:
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Val == INT32_MIN;
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}
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bool isMemTBB() const {
|
||||
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
|
||||
if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
|
||||
Mem.ShiftType != ARM_AM::no_shift)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
bool isMemTBH() const {
|
||||
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
|
||||
if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
|
||||
Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm != 1)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
bool isMemRegOffset() const {
|
||||
if (Kind != Memory || !Mem.OffsetRegNum)
|
||||
if (Kind != k_Memory || !Mem.OffsetRegNum)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
bool isT2MemRegOffset() const {
|
||||
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
|
||||
if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative)
|
||||
return false;
|
||||
// Only lsl #{0, 1, 2, 3} allowed.
|
||||
if (Mem.ShiftType == ARM_AM::no_shift)
|
||||
@ -738,14 +738,14 @@ public:
|
||||
bool isMemThumbRR() const {
|
||||
// Thumb reg+reg addressing is simple. Just two registers, a base and
|
||||
// an offset. No shifts, negations or any other complicating factors.
|
||||
if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
|
||||
if (Kind != k_Memory || !Mem.OffsetRegNum || Mem.isNegative ||
|
||||
Mem.ShiftType != ARM_AM::no_shift)
|
||||
return false;
|
||||
return isARMLowRegister(Mem.BaseRegNum) &&
|
||||
(!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
|
||||
}
|
||||
bool isMemThumbRIs4() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0 ||
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
|
||||
!isARMLowRegister(Mem.BaseRegNum))
|
||||
return false;
|
||||
// Immediate offset, multiple of 4 in range [0, 124].
|
||||
@ -754,7 +754,7 @@ public:
|
||||
return Val >= 0 && Val <= 124 && (Val % 4) == 0;
|
||||
}
|
||||
bool isMemThumbRIs2() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0 ||
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
|
||||
!isARMLowRegister(Mem.BaseRegNum))
|
||||
return false;
|
||||
// Immediate offset, multiple of 4 in range [0, 62].
|
||||
@ -763,7 +763,7 @@ public:
|
||||
return Val >= 0 && Val <= 62 && (Val % 2) == 0;
|
||||
}
|
||||
bool isMemThumbRIs1() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0 ||
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0 ||
|
||||
!isARMLowRegister(Mem.BaseRegNum))
|
||||
return false;
|
||||
// Immediate offset in range [0, 31].
|
||||
@ -772,7 +772,7 @@ public:
|
||||
return Val >= 0 && Val <= 31;
|
||||
}
|
||||
bool isMemThumbSPI() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
|
||||
return false;
|
||||
// Immediate offset, multiple of 4 in range [0, 1020].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -780,7 +780,7 @@ public:
|
||||
return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
|
||||
}
|
||||
bool isMemImm8s4Offset() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset a multiple of 4 in range [-1020, 1020].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -788,7 +788,7 @@ public:
|
||||
return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
|
||||
}
|
||||
bool isMemImm0_1020s4Offset() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset a multiple of 4 in range [0, 1020].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -796,7 +796,7 @@ public:
|
||||
return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
|
||||
}
|
||||
bool isMemImm8Offset() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset in range [-255, 255].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -804,7 +804,7 @@ public:
|
||||
return (Val == INT32_MIN) || (Val > -256 && Val < 256);
|
||||
}
|
||||
bool isMemPosImm8Offset() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset in range [0, 255].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -812,7 +812,7 @@ public:
|
||||
return Val >= 0 && Val < 256;
|
||||
}
|
||||
bool isMemNegImm8Offset() const {
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset in range [-255, -1].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -823,10 +823,10 @@ public:
|
||||
// If we have an immediate that's not a constant, treat it as a label
|
||||
// reference needing a fixup. If it is a constant, it's something else
|
||||
// and we reject it.
|
||||
if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
|
||||
if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
|
||||
return true;
|
||||
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset in range [0, 4095].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -837,10 +837,10 @@ public:
|
||||
// If we have an immediate that's not a constant, treat it as a label
|
||||
// reference needing a fixup. If it is a constant, it's something else
|
||||
// and we reject it.
|
||||
if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
|
||||
if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
|
||||
return true;
|
||||
|
||||
if (Kind != Memory || Mem.OffsetRegNum != 0)
|
||||
if (Kind != k_Memory || Mem.OffsetRegNum != 0)
|
||||
return false;
|
||||
// Immediate offset in range [-4095, 4095].
|
||||
if (!Mem.OffsetImm) return true;
|
||||
@ -848,7 +848,7 @@ public:
|
||||
return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
|
||||
}
|
||||
bool isPostIdxImm8() const {
|
||||
if (Kind != Immediate)
|
||||
if (Kind != k_Immediate)
|
||||
return false;
|
||||
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
|
||||
if (!CE) return false;
|
||||
@ -856,8 +856,8 @@ public:
|
||||
return (Val > -256 && Val < 256) || (Val == INT32_MIN);
|
||||
}
|
||||
|
||||
bool isMSRMask() const { return Kind == MSRMask; }
|
||||
bool isProcIFlags() const { return Kind == ProcIFlags; }
|
||||
bool isMSRMask() const { return Kind == k_MSRMask; }
|
||||
bool isProcIFlags() const { return Kind == k_ProcIFlags; }
|
||||
|
||||
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
|
||||
// Add as immediates when possible. Null MCExpr = 0.
|
||||
@ -1150,7 +1150,7 @@ public:
|
||||
|
||||
void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
|
||||
assert(N == 2 && "Invalid number of operands!");
|
||||
if (Kind == PostIndexRegister) {
|
||||
if (Kind == k_PostIndexRegister) {
|
||||
int32_t Val =
|
||||
ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
|
||||
Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
|
||||
@ -1216,7 +1216,7 @@ public:
|
||||
void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
|
||||
assert(N == 2 && "Invalid number of operands!");
|
||||
// If this is an immediate, it's a label reference.
|
||||
if (Kind == Immediate) {
|
||||
if (Kind == k_Immediate) {
|
||||
addExpr(Inst, getImm());
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
return;
|
||||
@ -1231,7 +1231,7 @@ public:
|
||||
void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
|
||||
assert(N == 2 && "Invalid number of operands!");
|
||||
// If this is an immediate, it's a label reference.
|
||||
if (Kind == Immediate) {
|
||||
if (Kind == k_Immediate) {
|
||||
addExpr(Inst, getImm());
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
return;
|
||||
@ -1346,7 +1346,7 @@ public:
|
||||
virtual void print(raw_ostream &OS) const;
|
||||
|
||||
static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(ITCondMask);
|
||||
ARMOperand *Op = new ARMOperand(k_ITCondMask);
|
||||
Op->ITMask.Mask = Mask;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1354,7 +1354,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(CondCode);
|
||||
ARMOperand *Op = new ARMOperand(k_CondCode);
|
||||
Op->CC.Val = CC;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1362,7 +1362,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(CoprocNum);
|
||||
ARMOperand *Op = new ARMOperand(k_CoprocNum);
|
||||
Op->Cop.Val = CopVal;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1370,7 +1370,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(CoprocReg);
|
||||
ARMOperand *Op = new ARMOperand(k_CoprocReg);
|
||||
Op->Cop.Val = CopVal;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1378,7 +1378,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(CCOut);
|
||||
ARMOperand *Op = new ARMOperand(k_CCOut);
|
||||
Op->Reg.RegNum = RegNum;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1386,7 +1386,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(Token);
|
||||
ARMOperand *Op = new ARMOperand(k_Token);
|
||||
Op->Tok.Data = Str.data();
|
||||
Op->Tok.Length = Str.size();
|
||||
Op->StartLoc = S;
|
||||
@ -1395,7 +1395,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(Register);
|
||||
ARMOperand *Op = new ARMOperand(k_Register);
|
||||
Op->Reg.RegNum = RegNum;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = E;
|
||||
@ -1407,7 +1407,7 @@ public:
|
||||
unsigned ShiftReg,
|
||||
unsigned ShiftImm,
|
||||
SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(ShiftedRegister);
|
||||
ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
|
||||
Op->RegShiftedReg.ShiftTy = ShTy;
|
||||
Op->RegShiftedReg.SrcReg = SrcReg;
|
||||
Op->RegShiftedReg.ShiftReg = ShiftReg;
|
||||
@ -1421,7 +1421,7 @@ public:
|
||||
unsigned SrcReg,
|
||||
unsigned ShiftImm,
|
||||
SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(ShiftedImmediate);
|
||||
ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
|
||||
Op->RegShiftedImm.ShiftTy = ShTy;
|
||||
Op->RegShiftedImm.SrcReg = SrcReg;
|
||||
Op->RegShiftedImm.ShiftImm = ShiftImm;
|
||||
@ -1432,7 +1432,7 @@ public:
|
||||
|
||||
static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
|
||||
SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(ShifterImmediate);
|
||||
ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
|
||||
Op->ShifterImm.isASR = isASR;
|
||||
Op->ShifterImm.Imm = Imm;
|
||||
Op->StartLoc = S;
|
||||
@ -1441,7 +1441,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(RotateImmediate);
|
||||
ARMOperand *Op = new ARMOperand(k_RotateImmediate);
|
||||
Op->RotImm.Imm = Imm;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = E;
|
||||
@ -1450,7 +1450,7 @@ public:
|
||||
|
||||
static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
|
||||
SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
|
||||
ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
|
||||
Op->Bitfield.LSB = LSB;
|
||||
Op->Bitfield.Width = Width;
|
||||
Op->StartLoc = S;
|
||||
@ -1461,13 +1461,13 @@ public:
|
||||
static ARMOperand *
|
||||
CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
|
||||
SMLoc StartLoc, SMLoc EndLoc) {
|
||||
KindTy Kind = RegisterList;
|
||||
KindTy Kind = k_RegisterList;
|
||||
|
||||
if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
|
||||
Kind = DPRRegisterList;
|
||||
Kind = k_DPRRegisterList;
|
||||
else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
|
||||
contains(Regs.front().first))
|
||||
Kind = SPRRegisterList;
|
||||
Kind = k_SPRRegisterList;
|
||||
|
||||
ARMOperand *Op = new ARMOperand(Kind);
|
||||
for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
|
||||
@ -1480,7 +1480,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(Immediate);
|
||||
ARMOperand *Op = new ARMOperand(k_Immediate);
|
||||
Op->Imm.Val = Val;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = E;
|
||||
@ -1488,7 +1488,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
|
||||
ARMOperand *Op = new ARMOperand(FPImmediate);
|
||||
ARMOperand *Op = new ARMOperand(k_FPImmediate);
|
||||
Op->FPImm.Val = Val;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1502,7 +1502,7 @@ public:
|
||||
unsigned ShiftImm,
|
||||
bool isNegative,
|
||||
SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(Memory);
|
||||
ARMOperand *Op = new ARMOperand(k_Memory);
|
||||
Op->Mem.BaseRegNum = BaseRegNum;
|
||||
Op->Mem.OffsetImm = OffsetImm;
|
||||
Op->Mem.OffsetRegNum = OffsetRegNum;
|
||||
@ -1518,7 +1518,7 @@ public:
|
||||
ARM_AM::ShiftOpc ShiftTy,
|
||||
unsigned ShiftImm,
|
||||
SMLoc S, SMLoc E) {
|
||||
ARMOperand *Op = new ARMOperand(PostIndexRegister);
|
||||
ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
|
||||
Op->PostIdxReg.RegNum = RegNum;
|
||||
Op->PostIdxReg.isAdd = isAdd;
|
||||
Op->PostIdxReg.ShiftTy = ShiftTy;
|
||||
@ -1529,7 +1529,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(MemBarrierOpt);
|
||||
ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
|
||||
Op->MBOpt.Val = Opt;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1537,7 +1537,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(ProcIFlags);
|
||||
ARMOperand *Op = new ARMOperand(k_ProcIFlags);
|
||||
Op->IFlags.Val = IFlags;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1545,7 +1545,7 @@ public:
|
||||
}
|
||||
|
||||
static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
|
||||
ARMOperand *Op = new ARMOperand(MSRMask);
|
||||
ARMOperand *Op = new ARMOperand(k_MSRMask);
|
||||
Op->MMask.Val = MMask;
|
||||
Op->StartLoc = S;
|
||||
Op->EndLoc = S;
|
||||
@ -1557,17 +1557,17 @@ public:
|
||||
|
||||
void ARMOperand::print(raw_ostream &OS) const {
|
||||
switch (Kind) {
|
||||
case FPImmediate:
|
||||
case k_FPImmediate:
|
||||
OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
|
||||
<< ") >";
|
||||
break;
|
||||
case CondCode:
|
||||
case k_CondCode:
|
||||
OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
|
||||
break;
|
||||
case CCOut:
|
||||
case k_CCOut:
|
||||
OS << "<ccout " << getReg() << ">";
|
||||
break;
|
||||
case ITCondMask: {
|
||||
case k_ITCondMask: {
|
||||
static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
|
||||
"(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
|
||||
"(tee)", "(eee)" };
|
||||
@ -1575,27 +1575,27 @@ void ARMOperand::print(raw_ostream &OS) const {
|
||||
OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
|
||||
break;
|
||||
}
|
||||
case CoprocNum:
|
||||
case k_CoprocNum:
|
||||
OS << "<coprocessor number: " << getCoproc() << ">";
|
||||
break;
|
||||
case CoprocReg:
|
||||
case k_CoprocReg:
|
||||
OS << "<coprocessor register: " << getCoproc() << ">";
|
||||
break;
|
||||
case MSRMask:
|
||||
case k_MSRMask:
|
||||
OS << "<mask: " << getMSRMask() << ">";
|
||||
break;
|
||||
case Immediate:
|
||||
case k_Immediate:
|
||||
getImm()->print(OS);
|
||||
break;
|
||||
case MemBarrierOpt:
|
||||
case k_MemBarrierOpt:
|
||||
OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
|
||||
break;
|
||||
case Memory:
|
||||
case k_Memory:
|
||||
OS << "<memory "
|
||||
<< " base:" << Mem.BaseRegNum;
|
||||
OS << ">";
|
||||
break;
|
||||
case PostIndexRegister:
|
||||
case k_PostIndexRegister:
|
||||
OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
|
||||
<< PostIdxReg.RegNum;
|
||||
if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
|
||||
@ -1603,7 +1603,7 @@ void ARMOperand::print(raw_ostream &OS) const {
|
||||
<< PostIdxReg.ShiftImm;
|
||||
OS << ">";
|
||||
break;
|
||||
case ProcIFlags: {
|
||||
case k_ProcIFlags: {
|
||||
OS << "<ARM_PROC::";
|
||||
unsigned IFlags = getProcIFlags();
|
||||
for (int i=2; i >= 0; --i)
|
||||
@ -1612,14 +1612,14 @@ void ARMOperand::print(raw_ostream &OS) const {
|
||||
OS << ">";
|
||||
break;
|
||||
}
|
||||
case Register:
|
||||
case k_Register:
|
||||
OS << "<register " << getReg() << ">";
|
||||
break;
|
||||
case ShifterImmediate:
|
||||
case k_ShifterImmediate:
|
||||
OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
|
||||
<< " #" << ShifterImm.Imm << ">";
|
||||
break;
|
||||
case ShiftedRegister:
|
||||
case k_ShiftedRegister:
|
||||
OS << "<so_reg_reg "
|
||||
<< RegShiftedReg.SrcReg
|
||||
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
|
||||
@ -1627,23 +1627,23 @@ void ARMOperand::print(raw_ostream &OS) const {
|
||||
<< ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
|
||||
<< ">";
|
||||
break;
|
||||
case ShiftedImmediate:
|
||||
case k_ShiftedImmediate:
|
||||
OS << "<so_reg_imm "
|
||||
<< RegShiftedImm.SrcReg
|
||||
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
|
||||
<< ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
|
||||
<< ">";
|
||||
break;
|
||||
case RotateImmediate:
|
||||
case k_RotateImmediate:
|
||||
OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
|
||||
break;
|
||||
case BitfieldDescriptor:
|
||||
case k_BitfieldDescriptor:
|
||||
OS << "<bitfield " << "lsb: " << Bitfield.LSB
|
||||
<< ", width: " << Bitfield.Width << ">";
|
||||
break;
|
||||
case RegisterList:
|
||||
case DPRRegisterList:
|
||||
case SPRRegisterList: {
|
||||
case k_RegisterList:
|
||||
case k_DPRRegisterList:
|
||||
case k_SPRRegisterList: {
|
||||
OS << "<register_list ";
|
||||
|
||||
const SmallVectorImpl<unsigned> &RegList = getRegList();
|
||||
@ -1656,7 +1656,7 @@ void ARMOperand::print(raw_ostream &OS) const {
|
||||
OS << ">";
|
||||
break;
|
||||
}
|
||||
case Token:
|
||||
case k_Token:
|
||||
OS << "'" << getToken() << "'";
|
||||
break;
|
||||
}
|
||||
@ -3640,8 +3640,8 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
||||
// ARM mode 'blx' need special handling, as the register operand version
|
||||
// is predicable, but the label operand version is not. So, we can't rely
|
||||
// on the Mnemonic based checking to correctly figure out when to put
|
||||
// a CondCode operand in the list. If we're trying to match the label
|
||||
// version, remove the CondCode operand here.
|
||||
// a k_CondCode operand in the list. If we're trying to match the label
|
||||
// version, remove the k_CondCode operand here.
|
||||
if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
|
||||
static_cast<ARMOperand*>(Operands[2])->isImm()) {
|
||||
ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user